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evollabs tech.

<div style="color: black;">
<div style="color: black;">Location: Dubai, United Arab Emirates</div>
<div style="color: black;">Employment: Full-time | On-site<br><br></div>
<div style="color: black;"><span class="large" style="font-size: 1.125rem; color: black;">Your Mission</span></div>
<div style="color: black;">Own the development and bring-up of hardware emulation environments for next-&nbsp;generation AI/HPC SoCs. You'll enable full-system validation, accelerate&nbsp;hardware/software integration, and support early firmware and software&nbsp;development before silicon is available. Working across RTL, verification, and&nbsp;software teams, you'll help identify complex system-level issues early and drive our&nbsp;AI silicon to&nbsp;ward successful tape-out.</div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;"><span class="large" style="font-size: 1.125rem; color: black;">Responsibilities</span></div>
<ul>
<li style="color: black;">Own SoC emulation: Build, integrate, and maintain subsystem and full-chip&nbsp;emulation environments using commercial hardware emulation platforms.</li>
<li style="color: black;">RTL bring-up and optimization: Compile, partition, map, and optimize RTL designs&nbsp;for emulation, resolving compatibility, performance, and integration issues.</li>
<li style="color: black;">Verification acceleration: Adapt UVM environments, develop BFMs and&nbsp;transactors, and enable hardware-accelerated verification.</li>
<li style="color: black;">HW/SW co-verification: Enable processor boot, firmware execution, driver&nbsp;development, and software-driven system validation.</li>
<li style="color: black;">System-level debugging: Investigate complex&nbsp;issues across CPU, NoC, DMA,&nbsp;memory, high-speed interfaces, and peripheral subsystems.</li>
<li style="color: black;">Automation and infrastructure: Develop reliable emulation build flows,&nbsp;regressions, CI integration, and debugging automation.</li>
<li style="color: black;">Integration and collaboration: Support third-party IP integration, maintain&nbsp;reproducible environments, and drive issues to resolution across engineering&nbsp;teams.</li>
</ul>
<div style="color: black;">You'll Collaborate With&nbsp;SoC architects, RTL designers, Functional Verification engineers, Firmware and</div>
<div style="color: black;">Software teams, and EDA/CAD engineers to enable early system validation, improve&nbsp;emulation performance, and accelerate pre-silicon development.<br><br></div>
<div style="color: black;"><span class="large" style="font-size: 1.125rem; color: black;">Minimum Qualifications</span></div>
<ul>
<li style="color: black;">7+ years of ASIC/SoC design, verification, or emulation experience, with&nbsp;substantial hands-on hardware emulation experience.</li>
<li style="color: black;">Proven experience with commercial hardware emulation platforms such as&nbsp;Cadence Palladium, Synopsys ZeBu, or Siemens Veloce.</li>
<li style="color: black;">Demonstrated ownership of subsystem or full-SoC emulation bring-up, from RTL&nbsp;compilation and mapping to execution and debugging.</li>
<li style="color: black;">Strong knowledge of Verilog/SystemVerilog, SoC architecture, and AMB&nbsp;protocols (AXI/APB).</li>
<li style="color: black;">Experience with emulation-compatible test environments, BFMs, transactors, and&nbsp;system-level debugging.</li>
<li style="color: black;">Good understanding of CPU subsystems, NoC/interconnect, DMA, memory&nbsp;systems, clocks, resets, and interrupts.</li>
<li style="color: black;">Proficiency in C/C++, Python, Tcl/Bash, Linux, and automation workflows.</li>
<li style="color: black;">Experience supporting firmware-driven verification and hardware/software&nbsp;integration.</li>
</ul>
<div style="color: black;"><span class="large" style="font-size: 1.125rem; color: black;">Preferred (Nice-to-Haves)</span></div>
<ul>
<li style="color: black;">Experience with UVM acceleration, SCE-MI, DPI-C, and transaction-based&nbsp;emulation.</li>
<li style="color: black;">Experience with RISC-V/ARM processors, JTAG, boot flows, and embedded&nbsp;firmware.</li>
<li style="color: black;">Exposure to&nbsp;AI accelerators, HPC SoCs, PCIe, Ethernet, CXL, UCIe, or advanced&nbsp;memory architectures.</li>
<li style="color: black;">Experience with FPGA prototyping, virtual platforms, or hybrid&nbsp;simulation/emulation environments.</li>
<li style="color: black;">Experience with multi-die SoCs, low-power validation, or post-silicon bring-up.</li>
</ul>
<div style="color: black;">&nbsp;</div>
</div>

Dubai Office

<div style="color: black;">
<div style="color: black;"><strong>Location:</strong> Dubai - UAE<br><strong>Team:</strong> IT Infrastructure / DevOps<br><strong>Type:</strong> Full-time - On-site<br><br></div>
<div style="color: black;"><span class="large bold" style="font-size: 1.125rem; color: black; font-weight: bold;"><strong>About Us</strong></span></div>
<div style="color: black;">We are a tech company specializing in the design and development of cutting-edge, customized server hardware solutions optimized for artificial intelligence and machine learning applications.<br>Our mission is to empower businesses and researchers to accelerate their AI initiatives by providing them with high-performance, scalable, and energy-efficient hardware infrastructure.</div>
<div style="color: black;">As a rapidly growing company at the forefront of AI hardware innovation, we are constantly seeking talented and motivated individuals to join our team. We offer a dynamic and challenging work environment, with opportunities to make a significant impact on the future of AI technology.<br><br></div>
<div style="color: black;"><span class="large bold" style="font-size: 1.125rem; color: black; font-weight: bold;"><strong>Your Mission</strong></span></div>
<div style="color: black;">As an <strong>ASIC EDA Flow Specialist</strong>, you will be responsible for architecting, developing, and maintaining the design flows and infrastructure that power our AI ASIC development. You will partner closely with RTL, verification, physical design, and CAD engineers to build robust, scalable, and efficient EDA environments that accelerate the path from RTL to silicon.<br>Your expertise will ensure our teams can innovate faster, with best-in-class automation, quality of results, and time-to-tape-out.<br><br></div>
<div style="color: black;"><span class="large bold" style="font-size: 1.125rem; color: black; font-weight: bold;"><strong>Responsibilities</strong></span></div>
<ul>
<li style="color: black;">
<div style="color: black;">Develop, maintain, and optimize <strong>ASIC EDA flows</strong> across front-end, back-end, and sign-off stages from RTL to GDS.</div>
</li>
<li style="color: black;">
<div style="color: black;">Manage <strong>EDA tool installations, updates, and license servers</strong> (FlexLM, RLM, SCL), including license forecasting, allocation, and vendor coordination.</div>
</li>
<li style="color: black;">
<div style="color: black;">Oversee <strong>compute grid and storage infrastructure</strong>, ensuring optimal job scheduling, resource utilization, and uptime for large-scale ASIC builds.</div>
</li>
<li style="color: black;">
<div style="color: black;">Architect and maintain <strong>Git-based infrastructure</strong> (GitLab) for design version control, CI/CD, and team collaboration.</div>
</li>
<li style="color: black;">
<div style="color: black;">Manage and support <strong>IP vendor tools</strong>, including evaluation, installation, and maintenance of vendor-specific environments (e.g., TSMC, ARM, Synopsys, Cadence).</div>
</li>
<li style="color: black;">
<div style="color: black;">Coordinate and track <strong>Soft and Hard IP integration</strong> within EDA flows, managing deliverables, versioning, and quality checks.</div>
</li>
<li style="color: black;">
<div style="color: black;">Maintain a central IP database with metadata (version, PDK, constraints, verification status) to streamline reuse across projects.</div>
</li>
<li style="color: black;">
<div style="color: black;">Collaborate with design teams to integrate third-party IPs into custom SoC flows and validate tool/IP compatibility.</div>
</li>
<li style="color: black;">
<div style="color: black;">Automate repetitive setup tasks (e.g., IP import, constraint generation, regression setup, reporting) to improve productivity.</div>
</li>
<li style="color: black;">
<div style="color: black;">Develop and maintain dashboards for EDA tool usage, license consumption, and compute/storage monitoring.</div>
</li>
<li style="color: black;">
<div style="color: black;">Document flow methodologies and provide internal training for new engineers.</div>
</li>
</ul>
<div style="color: black;"><span class="large bold" style="font-size: 1.125rem; color: black; font-weight: bold;"><strong>Requirements (must-have)</strong></span></div>
<ul>
<li style="color: black;">
<div style="color: black;">Bachelor&rsquo;s or Master&rsquo;s degree in Electrical Engineering, Computer Engineering, or a related field.</div>
</li>
<li style="color: black;">
<div style="color: black;">7 + years of experience in ASIC/SoC design environment management, CAD/EDA flow development, or design infrastructure engineering.</div>
</li>
<li style="color: black;">
<div style="color: black;">Strong knowledge of <strong>EDA tools</strong> (Synopsys, Cadence, Siemens/Mentor) and their installation, configuration, and licensing.</div>
</li>
<li style="color: black;">
<div style="color: black;">Experience with <strong>EDA license servers</strong> (FlexLM, RLM, SCL) and usage optimization.</div>
</li>
<li style="color: black;">
<div style="color: black;">Proficiency in <strong>Tcl, Python, Yaml, and Shell scripting</strong> for automation and flow development.</div>
</li>
<li style="color: black;">
<div style="color: black;">Proficiency in <strong>Make, CMake, or Bazel-based orchestration frameworks</strong> for flow and regression builds.</div>
</li>
<li style="color: black;">
<div style="color: black;">Familiarity with <strong>compute grid management systems</strong> (LSF, SLURM, Grid Engine) and <strong>storage architecture</strong> for large ASIC projects.</div>
</li>
<li style="color: black;">
<div style="color: black;">Practical experience with <strong>Git</strong> and integration into design workflows.</div>
</li>
<li style="color: black;">
<div style="color: black;">Proficiency in <strong>CI/CD automation</strong>, pipelines, or internal build systems.</div>
</li>
<li style="color: black;">
<div style="color: black;">Strong communication, documentation, and problem-solving skills.</div>
</li>
</ul>
<div style="color: black;"><span class="large bold" style="font-size: 1.125rem; color: black; font-weight: bold;"><strong>Nice-to-Have</strong></span></div>
<ul>
<li style="color: black;">
<div style="color: black;">Solid understanding of RTL-to-GDSII flow, timing/power trade-offs, and tool interactions.</div>
</li>
<li style="color: black;">
<div style="color: black;">Exposure to <strong>advanced process nodes</strong> (7 nm and below) and multi-die design methodologies.</div>
</li>
</ul>
<div style="color: black;"><span class="normal bold" style="font-size: 0.8125rem; color: black; font-weight: bold;"><strong>Why Join Us</strong></span></div>
<ul>
<li style="color: black;">
<div style="color: black;">Work at the intersection of <strong>AI and silicon</strong> to enable breakthroughs that power the next generation of intelligent computing.</div>
</li>
<li style="color: black;">
<div style="color: black;">Join a highly experienced, fast-moving team that values <strong>technical depth</strong>, <strong>innovation</strong>, and <strong>hands-on impact</strong>.</div>
</li>
<li style="color: black;">
<div style="color: black;">Build and own EDA methodologies that directly influence silicon performance, cost, and scalability.</div>
</li>
<li style="color: black;">
<div style="color: black;">Enjoy an environment that rewards <strong>initiative</strong>, <strong>collaboration</strong>, and <strong>continuous learning</strong>.</div>
</li>
<li style="color: black;">
<div style="color: black;">Competitive compensation, growth opportunities, and the chance to shape the core infrastructure behind cutting-edge AI ASICs.</div>
</li>
</ul>
<div style="color: black;"><span class="normal bold" style="font-size: 0.8125rem; color: black; font-weight: bold;"><strong>Ready to Accelerate the Future of AI?</strong></span></div>
<div style="color: black;">If you&rsquo;re passionate about building world-class design flows and enabling engineers to push the limits of silicon performance, we&rsquo;d love to hear from you.<br>Apply now and join us on our journey to redefine AI hardware performance at scale.</div>
</div>

<div style="color: black;">
<div style="color: black;"><strong>Description</strong></div>
<div style="color: black;">We are a technology company focused on designing and developing advanced, customized server hardware solutions optimized for artificial intelligence workloads. Our mission is to accelerate AI innovation by delivering high-performance, scalable, and energy-efficient infrastructure for datacenter-scale inference. Our chips in development are purpose-built for large-scale AI inference and will be deployed in rack-level systems where multiple devices collaborate to deliver optimal latency, throughput, and efficiency. We are building the next generation of AI infrastructure and are looking for engineers who deeply understand high-performance networking, collective communication, and distributed AI systems.</div>
<div style="color: black;">&nbsp;<br>This role is focused on designing and implementing collective communication support for our AI accelerator platform, including both NPU-native communication and heterogeneous NPU-GPU communication. You will work at the intersection of accelerator runtime, networking, distributed AI workloads, and hardware-software co-design.</div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;"><strong>Responsibilities</strong></div>
<div style="color: black;">&bull; Design and implement collective communication primitives for AI accelerators.</div>
<div style="color: black;">&bull; Build NPU-native CCL support for multi-chip and rack-scale AI inference systems.</div>
<div style="color: black;">&bull; Design and implement heterogeneous NPU-GPU communication paths for distributed AI workloads.</div>
<div style="color: black;">&bull; Develop communication runtime components for device discovery, rank management, topology awareness, stream/queue integration, events, and synchronization.</div>
<div style="color: black;">&bull; Work on transport-layer integration across PCIe, Ethernet/RDMA, custom accelerator fabrics, or other device-to-device communication mechanisms.</div>
<div style="color: black;">&bull; Collaborate with hardware, runtime, compiler, and model-serving teams to co-design scalable communication paths for AI workloads.</div>
<div style="color: black;">&bull; Profile, debug, and optimize communication bottlenecks including bandwidth, latency, congestion, synchronization overhead, and compute-communication overlap.</div>
<div style="color: black;">&bull; Build correctness, performance, and stress tests for multi-device and heterogeneous communication scenarios.Requirements</div>
<div style="color: black;">&bull; 5+ years of relevant experience with M.S./Ph.D. degree in CS/CE or equivalent experience.</div>
<div style="color: black;">&bull; Strong C/C++ and python programming skills with experience building low-level runtime, driver, networking, or distributed systems software.</div>
<div style="color: black;">&bull; Deep understanding of collective communication primitives such as AllReduce, ReduceScatter, AllGather, AllToAll, Broadcast, Send/Recv, and Barrier.</div>
<div style="color: black;">&bull; Familiarity with any networking and distributed communication libraries such as NCCL, RCCL, oneCCL, MPI, UCX, or libfabric.</div>
<div style="color: black;">&bull; Strong knowledge of GPU/NPU memory models, accelerator memory allocation, memory registration, peer-to-peer transfers, and heterogeneous device communication.</div>
<div style="color: black;">&bull; Experience with accelerator runtime concepts such as queues, streams, events, command submission, completion handling, synchronization, and memory management.</div>
<div style="color: black;">&bull; Strong understanding of hardware-software interaction in accelerator systems, including DMA engines, device memory, interrupts, doorbells, fences, and completion signaling.</div>
<div style="color: black;">&bull; Knowledge of high-performance networking like InfiniBand, and RoCE.</div>
<div style="color: black;">&bull; Ability to work close to hardware, including DMA engines, queues, streams, fences, completion signaling, NoC/fabric behavior, and accelerator runtime integration.</div>
<div style="color: black;">&bull; Strong performance engineering skills for optimizing bandwidth, latency, synchronization overhead, congestion, and compute-communication overlap.</div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;"><strong>Nice to Have</strong></div>
<div style="color: black;">&bull; Familiarity with PyTorch distributed backends, custom ProcessGroup implementations, or distributed framework integration.</div>
<div style="color: black;">&bull; Experience optimizing communication for LLM workloads, including tensor parallelism, MoE expert parallelism, KV-cache transfer, or disaggregated inference.</div>
<div style="color: black;">&bull; Experience integrating communication backends with distributed AI frameworks or serving systems such as PyTorch distributed, vLLM, SGLang, or similar platforms.</div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;"><strong>What We're Not Looking For</strong></div>
<div style="color: black;">This role is not focused on general backend networking, web services, prompt engineering, or application-layer GenAI development. Instead, it is centered on low-level collective communication, accelerator runtime, heterogeneous device communication, and distributed AI performance at scale.</div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;"><strong>Why Join Us?</strong></div>
<div style="color: black;">&bull; Work on cutting-edge AI hardware designed specifically for large-scale inference</div>
<div style="color: black;">&bull; Build core communication infrastructure for next-generation NPU and heterogeneous NPU-GPU systems.</div>
<div style="color: black;">&bull; Solve challenging problems at the intersection of AI accelerators, networking, distributed runtime, and datacenter-scale systems.</div>
<div style="color: black;">&bull; Collaborate with hardware, compiler, runtime, and model-serving teams on a full-stack AI infrastructure platform.</div>
<div style="color: black;">&bull; Make a direct impact on the scalabili</div>
</div>

India Office

<div style="color: black;">
<div style="color: black;"><span class="normal bold" style="font-size: 0.8125rem; color: black; font-weight: bold;">About the Role<br><br></span></div>
<div style="color: black;">Join us to build the <strong>next-generation Network Operating System (NOS)</strong> powering cutting-edge switches and routers for global data centers and telco providers. As part of our <strong>Hardware Abstraction Layer (HAL)</strong> team, you&rsquo;ll work directly with advanced <strong>ASICs from leading vendors</strong> and help bridge the gap between hardware and software in high-performance networking gear.</div>
<div style="color: black;">This is a unique opportunity to work on a <strong>greenfield NOS/NMS suite</strong> with AI-enhanced features, backed by one of the world&rsquo;s largest and most recognized ODMs &mdash; but with the freedom and speed of a startup.</div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;"><span class="normal bold" style="font-size: 0.8125rem; color: black; font-weight: bold;">What You&rsquo;ll Do</span></div>
<ul>
<li style="color: black;">
<div style="color: black;">Design and implement NOS components that program and manage advanced network ASICs.</div>
</li>
<li style="color: black;">
<div style="color: black;">Debug, optimize, and improve multithreaded C code running on Linux-based systems.</div>
</li>
<li style="color: black;">
<div style="color: black;">Collaborate with hardware engineers to integrate drivers, SDKs, and chip features seamlessly.</div>
</li>
<li style="color: black;">
<div style="color: black;">Work with control-plane teams to translate BGP, OSPF, MPLS, and other routing protocols into hardware behavior.</div>
</li>
<li style="color: black;">
<div style="color: black;">Participate in design reviews and champion engineering best practices.</div>
</li>
<li style="color: black;">
<div style="color: black;">Support QA teams in building automated tests for ASIC-facing software components.</div>
</li>
</ul>
<div style="color: black;"><span class="normal bold" style="font-size: 0.8125rem; color: black; font-weight: bold;">What We&rsquo;re Looking For</span></div>
<ul>
<li style="color: black;">
<div style="color: black;">Degree (or equivalent experience) in Computer Science, Electrical Engineering, or related field.</div>
</li>
<li style="color: black;">
<div style="color: black;">Strong C programming skills and experience with Linux OS internals.</div>
</li>
<li style="color: black;">
<div style="color: black;">Knowledge of Ethernet/IP protocols and at least one dynamic routing protocol (BGP, OSPF).</div>
</li>
<li style="color: black;">
<div style="color: black;">Ability to read standards (IETF RFCs, IEEE) and translate them into working code.</div>
</li>
<li style="color: black;">
<div style="color: black;">Hands-on debugging experience with complex, multithreaded systems.</div>
</li>
<li style="color: black;">
<div style="color: black;">Ability to navigate large-scale codebases (&gt;3GB).</div>
</li>
</ul>
<div style="color: black;"><span class="normal bold" style="font-size: 0.8125rem; color: black; font-weight: bold;">Ways to Stand Out</span></div>
<ul>
<li style="color: black;">
<div style="color: black;">Experience with <strong>Broadcom StrataDNX</strong> or similar ASIC SDKs.</div>
</li>
<li style="color: black;">
<div style="color: black;">Familiarity with Linux kernel networking stack.</div>
</li>
<li style="color: black;">
<div style="color: black;">Exposure to I2C, SMBus/PMBus, ACPI, CPLDs, or FPGA-based systems.</div>
</li>
<li style="color: black;">
<div style="color: black;">Prior work on multithreaded Linux daemons and embedded platforms.</div>
</li>
<li style="color: black;">
<div style="color: black;">Experience with virtualization/containerization (KVM, Docker, Kubernetes).</div>
</li>
</ul>
</div>

<div style="color: black;">
<div style="color: black;"><span class="large bold" style="font-size: 1.125rem; color: black; font-weight: bold;">About Us</span></div>
<div style="color: black;">We are a tech company specializing in the design and development of cutting-edge, customized server hardware solutions optimized for artificial intelligence and machine learning applications. Our mission is to empower businesses and researchers to accelerate their AI initiatives by providing them with high-performance, scalable, and energy-efficient hardware infrastructure.</div>
<div style="color: black;">As a rapidly growing company at the forefront of AI hardware innovation, we are constantly seeking talented and motivated individuals to join our team. We offer a dynamic and challenging work environment, with opportunities to make a significant impact on the future of AI technology.</div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;"><span class="large bold" style="font-size: 1.125rem; color: black; font-weight: bold;">Your Mission</span></div>
<div style="color: black;">Build the low-level firmware foundation that brings our next-generation AI training ASIC to life &mdash; from secure boot to runtime management, PCIe bring-up to multi-die coordination. Your code will be the critical bridge between our custom silicon and the AI workloads that will reshape industries. This is where hardware meets software, where every microsecond matters, and where your expertise directly accelerates AI breakthroughs for our customers worldwide.</div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;"><span class="large bold" style="font-size: 1.125rem; color: black; font-weight: bold;">What You'll Own</span></div>
<ul>
<li style="color: black;">
<div style="color: black;"><strong>Boot &amp; Security</strong>: Implement our secure boot chain (BootROM &rarr; PBL/SBL &rarr; RTOS), device identity, attestation, anti-rollback, and field updates that protect our customers' valuable AI models and data.</div>
</li>
<li style="color: black;">
<div style="color: black;"><strong>Hardware Bring-Up</strong>: Initialize clocks, power, HBM, PCIe, NoC, and SerDes PHYs &mdash; often before our silicon arrives (emulation/FPGA), ensuring first-time-right deployment.</div>
</li>
<li style="color: black;">
<div style="color: black;"><strong>High-Speed Networking</strong>: Bring up 400G Ethernet interfaces, configure MAC/PCS/FEC layers, and coordinate with network stack for RDMA offload engines essential for distributed AI training.</div>
</li>
<li style="color: black;">
<div style="color: black;"><strong>Runtime Excellence</strong>: Power/thermal control, DVFS, watchdogs, RAS (ECC, crash dumps), and error recovery that delivers the 99.99% uptime our datacenter customers demand.</div>
</li>
<li style="color: black;">
<div style="color: black;"><strong>Host Communication</strong>: Design mailbox protocols, MSI/MSI-X, DMA coordination, and health reporting with our Linux driver team to enable seamless integration.</div>
</li>
<li style="color: black;">
<div style="color: black;"><strong>Telemetry &amp; Observability</strong>: Unified event tracing with synchronized timestamps (PTP/PHC) giving our customers unprecedented visibility into their AI infrastructure.</div>
</li>
<li style="color: black;">
<div style="color: black;"><strong>Multi-Die Scaling</strong>: Discovery, link training, topology management, and load-balancing hooks across chiplets &mdash; because AI models keep growing.</div>
</li>
<li style="color: black;">
<div style="color: black;"><strong>Validation &amp; Documentation</strong>: Own bring-up guides, scripted tests, HIL/emulation validation, and HAL/config schemas that enable our global support team and customers.</div>
</li>
</ul>
<div style="color: black;"><span class="large bold" style="font-size: 1.125rem; color: black; font-weight: bold;">You'll Collaborate With</span></div>
<div style="color: black;">Our silicon architects designing the next breakthrough in AI compute, Linux driver engineers building the software stack, security teams protecting customer assets, and system validation engineers ensuring enterprise reliability &mdash; together, we're building the infrastructure that makes AI accessible and powerful.</div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;"><span class="large bold" style="font-size: 1.125rem; color: black; font-weight: bold;">Required Qualifications</span></div>
<ul>
<li style="color: black;">
<div style="color: black;">5+ years embedded firmware (C/C++/Rust) on ASIC/SoC or GPU-like accelerators</div>
</li>
<li style="color: black;">
<div style="color: black;">Proven experience with one of the complex high-speed subsystems <strong>is a must</strong>: PCIe bring-up (enumeration, BARs, MSI-X, DMA engines), memory subsystems (HBM/GDDR/DDR), high-speed Ethernet 100G+</div>
</li>
<li style="color: black;">
<div style="color: black;">Configuration and management of clock/power domains, and RAS features</div>
</li>
<li style="color: black;">
<div style="color: black;">Comfortable reading schematics, register specs, and debugging with JTAG/logic analyzers</div>
</li>
<li style="color: black;">
<div style="color: black;">Strong documentation and code review habits &mdash; your code will be the foundation others build upon</div>
</li>
<li style="color: black;">
<div style="color: black;">Systems thinking: understanding how firmware decisions impact the full stack from silicon to application</div>
</li>
</ul>
<div style="color: black;"><span class="large bold" style="font-size: 1.125rem; color: black; font-weight: bold;">Preferred (Nice-to-Haves)</span></div>
<ul>
<li style="color: black;">
<div style="color: black;">RISC-V/ARM64 + TrustZone/TEE or secure enclave development</div>
</li>
<li style="color: black;">
<div style="color: black;">400G Ethernet firmware experience: MAC/PCS configuration, FEC modes, RDMA/RoCE offload, and 56G/112G SerDes bring-up</div>
</li>
<li style="color: black;">
<div style="color: black;">Hands-on with secure boot (UEFI/coreboot/PBL/SBL) and cryptographic signing/verification</div>
</li>
<li style="color: black;">
<div style="color: black;">Secure provisioning (OTP/fuses, cert injection) for production deployment</div>
</li>
<li style="color: black;">
<div style="color: black;">QEMU/virtual platform pre-silicon development experience</div>
</li>
<li style="color: black;">
<div style="color: black;">Linux driver interfaces (debugfs, sysfs, mailbox) coordination</div>
</li>
<li style="color: black;">
<div style="color: black;">Compliance (UEFI/ACPI/PCIe), SBOM, or safety certifications</div>
</li>
<li style="color: black;">
<div style="color: black;">Experience with systematic design approaches (INCOSE principles, V-model, requirements traceability)</div>
</li>
</ul>
<div style="color: black;"><span class="large bold" style="font-size: 1.125rem; color: black; font-weight: bold;">Success in 6&ndash;9 Months</span></div>
<ul>
<li style="color: black;" data-type="checkbox_item">
<div id="checkbox-be3d7bfa-3c08-491d-9f32-f67c4a04c20a" style="color: black;">
<div style="color: black;">Secure boot &amp; OTA update flow validated on FPGA/emulation &mdash; customer data protected from day one</div>
</div>
</li>
<li style="color: black;" data-type="checkbox_item">
<div id="checkbox-c200c9c0-79e2-43de-882e-67e6e6e9ec4a" style="color: black;">
<div style="color: black;">PCIe + mailbox protocol stable under stress with Linux driver &mdash; plug-and-play in any datacenter</div>
</div>
</li>
<li style="color: black;" data-type="checkbox_item">
<div id="checkbox-43ad496c-1909-4eba-8fe3-b9c410ae5a7a" style="color: black;">
<div style="color: black;">Runtime services (power/thermal/DVFS) telemetry-rich and reliable &mdash; meeting SLA requirements</div>
</div>
</li>
<li style="color: black;" data-type="checkbox_item">
<div id="checkbox-becd1256-72f0-423e-82aa-366a500995aa" style="color: black;">
<div style="color: black;">Unified tracing with synchronized timestamps exposed to host &mdash; full stack observability achieved</div>
</div>
</li>
<li style="color: black;" data-type="checkbox_item">
<div id="checkbox-18de8ffa-1e99-4dd3-b5d4-f5815c837c53" style="color: black;">
<div style="color: black;">Bring-up docs + automated validation cover golden paths &amp; recovery &mdash; enabling global deployment</div>
</div>
</li>
</ul>
<div style="color: black;"><span class="large bold" style="font-size: 1.125rem; color: black; font-weight: bold;">Our Development Approach</span></div>
<div style="color: black;">We believe firmware is mission-critical infrastructure that demands both innovation and rigor. We invest in architecture, testing, and standards compliance because our customers depend on our platform to run their most important AI workloads. We move fast when prototyping, but we measure twice and cut once when it comes to production firmware.</div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;"><span class="large bold" style="font-size: 1.125rem; color: black; font-weight: bold;">Tools &amp; Standards We Use</span></div>
<div style="color: black;"><strong>Build &amp; CI:</strong> CMake/Bazel, GitLab CI/CD, Coverity, PC-lint<br><strong>Debug &amp; Validation:</strong> OpenOCD/pyOCD, JTAG/SWD, logic analyzers, QEMU/emulation<br><strong>Standards:</strong> PCIe 5.0, 400GbE/IEEE 802.3, UEFI/ACPI where applicable, TCG security guidelines<br><strong>Languages:</strong> C17/Rust, Python (tooling/testing)</div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;"><span class="large bold" style="font-size: 1.125rem; color: black; font-weight: bold;">Why This Role Matters</span></div>
<div style="color: black;">The AI revolution needs more than just algorithms &mdash; it needs the high-performance, energy-efficient hardware to run them at scale. Your firmware expertise will directly enable researchers to train larger models, businesses to deploy AI faster, and innovators to push the boundaries of what's possible. This isn't just another embedded role; it's your chance to build the foundation of AI infrastructure that will power the next decade of technological advancement.</div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;"><strong>Ready to accelerate the future of AI from the firmware up?</strong></div>
<div style="color: black;">Submit your application with links to relevant firmware projects, papers, or upstream contributions demonstrating secure boot, update/recovery, PCIe bring-up, or runtime management. Show us how you think systematically about firmware architecture and what you've built that scales.</div>
<div style="color: black;"><em style="color: black;">Join us in our mission to democratize AI compute &mdash; where your firmware expertise becomes the bedrock of tomorrow's AI breakthroughs.</em></div>
</div>

<div style="color: black;">
<div style="color: black;">Location: Dubai - UAE</div>
<div style="color: black;">Team: Hardware Engineering &ndash; Package Design &amp; Bring-Up</div>
<div style="color: black;">Type: Full-time &ndash; On-site<br><br></div>
<div style="color: black;"><strong>About Us</strong></div>
<div style="color: black;">We are a tech company specializing in the design and development of cutting-edge, customized&nbsp;server hardware solutions optimized for artificial intelligence and machine learning applications.&nbsp;Our mission is to empower businesses and researchers to accelerate their AI initiatives by&nbsp;providing them with high-performance, scalable, and energy-efficient hardware infrastructure.&nbsp;As a rapidly growing company at the forefront of AI hardware innovation, we are constantly&nbsp;seeking talented and motivated individuals to join our team. We offer a dynamic and challenging&nbsp;work environment, with opportunities to make a significant impact on the future of AI technology.</div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;"><strong>Your Mission</strong></div>
<div style="color: black;">As a Package Design Engineer, you will own the chip package of our AI accelerators end to&nbsp;end, from packaging technology selection and die/package/board co-design through substrate&nbsp;and interposer design, package-level test, and first-silicon bring-up. You will turn multi-chiplet&nbsp;silicon with demanding high-speed interfaces into robust, manufacturable, high-performance&nbsp;packages, working at the intersection of silicon design, signal and power integrity, thermal-mechanical engineering, and the foundry/OSAT supply chain.<br><br></div>
<div style="color: black;"><strong>Responsibilities</strong></div>
<div style="color: black;">&bull; Package architecture and technology selection: evaluate standard flip-chip BGA and&nbsp;advanced packaging options (2.5D silicon interposer, silicon bridge, fan-out, 3D&nbsp;stacking) against product requirements, and drive die/package/board co-optimization of&nbsp;floorplans, bump patterns, pad rings, and ball-out with silicon and system teams.</div>
<div style="color: black;">&bull; Multi-chiplet package design: own substrate and interposer design for multi-die&nbsp;assemblies, including netlist management, routing, layer stack-up definition, and design-rule compliance across compute, memory, and I/O chiplets.</div>
<div style="color: black;">&bull; High-speed interface packaging: deliver package channels that meet the budgets of&nbsp;PCIe Gen5/Gen6, 400/800G Ethernet (56G/112G PAM4 SerDes), HBM, and UCIe/BoW&nbsp;die-to-die links, collaborating with signal and power integrity engineers on extraction,&nbsp;simulation, and margin sign-off.</div>
<div style="color: black;">&bull; Power, thermal, and mechanical co-design: define the package PDN, decoupling&nbsp;strategy, and thermal solution for high-power accelerator silicon, and manage warpage,&nbsp;CTE mismatch, and reliability risks together with thermal-mechanical engineers.</div>
<div style="color: black;">&bull; Manufacturing and supply-chain execution: engage foundries, OSATs, and substrate&nbsp;suppliers on design rules, DFM feedback, assembly flows, qualification, and yield&nbsp;improvement, and drive package NPI from tape-out to production release.<br>&bull; Package test and silicon bring-up: define package-level test and characterization&nbsp;plans, support first-silicon bring-up in the lab, and lead package-related debug and&nbsp;failure analysis through to root cause and corrective action.</div>
<div style="color: black;">&bull; Cross-functional collaboration and documentation: write clear package&nbsp;specifications, design guidelines, and review material, and lead design reviews with&nbsp;silicon, board, SI/PI, thermal, and product engineering teams.<br><br></div>
<div style="color: black;"><strong>Requirements</strong></div>
<div style="color: black;">&bull; Bachelor&rsquo;s or Master&rsquo;s in Electrical Engineering, Materials Science, Mechanical&nbsp;Engineering, or related field.&nbsp;</div>
<div style="color: black;">&bull; 8+ years in semiconductor package design, with a strong focus on high-performance&nbsp;digital ASICs, GPUs, or AI accelerators.</div>
<div style="color: black;">&bull; Proven track record of taking complex multi-chiplet packages (2.5D interposer, silicon&nbsp;bridge, or fan-out based) from concept to production.</div>
<div style="color: black;">&bull; Hands-on experience with both standard flip-chip BGA and advanced packaging&nbsp;technologies such as CoWoS, EMIB, InFO/FoCoS, or equivalent foundry and OSAT&nbsp;platforms.</div>
<div style="color: black;">&bull; Package design experience for high-speed serial interfaces, specifically PCIe&nbsp;Gen5/Gen6 and 400/800G Ethernet, including breakout, escape routing, and channel&nbsp;budget ownership.</div>
<div style="color: black;">&bull; Experience with die-to-die interconnects such as UCIe or Bunch of Wires (BoW),&nbsp;including bump map definition, channel design, and routing rules for D2D links.</div>
<div style="color: black;">&bull; Experience integrating HBM or similar memory subsystems on interposer or bridge,&nbsp;including routing, stack-up, and assembly considerations.</div>
<div style="color: black;">&bull; Solid grounding in package signal and power integrity, transmission line theory, and&nbsp;PDN design, with the ability to drive and interpret extraction and simulation results.</div>
<div style="color: black;">&bull; Working knowledge of thermal and mechanical fundamentals for large-body, high-power&nbsp;packages, including warpage control and JEDEC reliability qualification.</div>
<div style="color: black;">&bull; Experience supporting package test, characterization, first-silicon bring-up, and failure&nbsp;analysis in collaboration with test and product engineering.</div>
<div style="color: black;">&bull; Proficiency with package EDA tools such as Cadence APD/SiP Layout or Synopsys&nbsp;3DIC Compiler, plus familiarity with SI/PI analysis tools (Ansys HFSS/SIwave, Cadence&nbsp;Clarity/Sigrity, or similar).</div>
<div style="color: black;">&bull; Excellent cross-functional communication and documentation skills, including experience&nbsp;working directly with foundry, OSAT, and substrate vendor engineering teams.&nbsp;<br><br><strong>Preferred Qualifications (Nice-to-Haves)</strong></div>
<div style="color: black;">&bull; Experience with 3D stacking and hybrid bonding technologies (SoIC, Foveros, or similar)&nbsp;and their design and test implications.</div>
<div style="color: black;">&bull; Exposure to co-packaged optics or photonics packaging for high-bandwidth I/O.</div>
<div style="color: black;">&bull; Experience defining packaging testchips and running technology qualification vehicles&nbsp;with foundry or OSAT partners.<br>&bull; Hands-on use of thermal and mechanical simulation tools (Ansys Icepak, Celsius,&nbsp;mechanical FEA) for package-level analysis.</div>
<div style="color: black;">&bull; Familiarity with UCIe compliance and interoperability testing, or participation in chiplet&nbsp;standards bodies (UCIe Consortium, OCP ODSA).</div>
<div style="color: black;">&bull; Experience managing OSAT and substrate vendor relationships, schedules, and cost&nbsp;trade-offs during NPI.<br><br></div>
<div style="color: black;"><strong>Why Join Us</strong></div>
<div style="color: black;">&bull; Own the package of a next-generation AI accelerator from first concept to working&nbsp;silicon, where your decisions directly set the product&rsquo;s performance, power, and cost.</div>
<div style="color: black;">&bull; Work in a tight cross-functional team of silicon, board, SI/PI, and thermal engineers that&nbsp;values technical depth and hands-on problem solving.</div>
<div style="color: black;">&bull; Cover the full scope in one role: architecture, design, supplier engagement, lab bring-up,&nbsp;and production ramp.</div>
<div style="color: black;">&bull; Competitive compensation, growth opportunities, and the chance to help define the&nbsp;platform that powers advanced AI workloads.<br><br></div>
<div style="color: black;"><strong>Ready to Accelerate the Future of AI?</strong></div>
<div style="color: black;">If you&rsquo;re passionate about turning multi-chiplet silicon into robust, high-performance packages</div>
<div style="color: black;">&mdash; we&rsquo;d love to hear from you.</div>
<div style="color: black;">Apply now and help us deliver production-ready platforms that make AI faster, safer, and more</div>
<div style="color: black;">efficient.</div>
</div>

<div style="color: black;">
<div style="color: black;"><span class="normal bold" style="font-size: 0.8125rem; color: black; font-weight: bold;">About the Role</span></div>
<div style="color: black;">As QA Team Lead, you will build and guide a team of QA Engineers and SDETs responsible for the <strong>quality of our NOS</strong>. You&rsquo;ll balance <strong>technical leadership</strong> (test strategy, automation design) with <strong>people leadership</strong> (mentorship, team development, delivery accountability).</div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;"><span class="normal bold" style="font-size: 0.8125rem; color: black; font-weight: bold;">What You&rsquo;ll Do</span></div>
<ul>
<li style="color: black;">
<div style="color: black;">Lead and mentor a QA team (5&ndash;10 engineers) across manual and automated testing.</div>
</li>
<li style="color: black;">
<div style="color: black;">Define QA strategy for functional, regression, and performance validation.</div>
</li>
<li style="color: black;">
<div style="color: black;">Oversee CI/CD pipeline integration of QA workflows.</div>
</li>
<li style="color: black;">
<div style="color: black;">Coordinate test planning with development leads across HAL, Control Plane, and Management Plane.</div>
</li>
<li style="color: black;">
<div style="color: black;">Ensure timely and high-quality delivery of test cycles.</div>
</li>
<li style="color: black;">
<div style="color: black;">Act as the voice of QA in release and architecture reviews.</div>
</li>
</ul>
<div style="color: black;"><span class="normal bold" style="font-size: 0.8125rem; color: black; font-weight: bold;">What We&rsquo;re Looking For</span></div>
<ul>
<li style="color: black;">
<div style="color: black;">Proven experience leading QA teams in networking or systems software.</div>
</li>
<li style="color: black;">
<div style="color: black;">Strong technical background in test automation and network engineering.</div>
</li>
<li style="color: black;">
<div style="color: black;">Familiarity with major routing protocols and data center networking.</div>
</li>
<li style="color: black;">
<div style="color: black;">Experience managing CI/CD-driven QA environments.</div>
</li>
<li style="color: black;">
<div style="color: black;">Excellent communication and leadership skills.</div>
</li>
</ul>
<div style="color: black;"><span class="normal bold" style="font-size: 0.8125rem; color: black; font-weight: bold;">Career Opportunity</span></div>
<div style="color: black;">You will <strong>own the quality culture</strong> of a greenfield NOS project &mdash; building not only a product but also a QA discipline that sets benchmarks for MENAT and beyond.</div>
<div style="color: black;">&nbsp;</div>
</div>

<div style="color: black;">
<div style="color: black;"><span class="normal bold" style="font-size: 0.8125rem; color: black; font-weight: bold;">About the Role<br></span></div>
<div style="color: black;">As Team Lead of the <strong>HAL Engineering group</strong>, you will guide a team of talented C engineers to deliver the software foundation of our NOS. You&rsquo;ll combine <strong>technical leadership</strong> with <strong>team mentorship</strong>, ensuring that the HAL layer is robust, performant, and future-proof.</div>
<div style="color: black;">This is both a hands-on and people-focused role: you&rsquo;ll still code, but also set direction, coach engineers, and drive execution.<br><br></div>
<div style="color: black;"><span class="normal bold" style="font-size: 0.8125rem; color: black; font-weight: bold;">What You&rsquo;ll Do</span></div>
<ul>
<li style="color: black;">
<div style="color: black;">Lead a team (10-15 engineers) delivering HAL components of the NOS.</div>
</li>
<li style="color: black;">
<div style="color: black;">Set priorities, review code, and enforce high-quality engineering practices.</div>
</li>
<li style="color: black;">
<div style="color: black;">Coordinate with hardware engineering, control plane, QA, and product teams.</div>
</li>
<li style="color: black;">
<div style="color: black;">Provide technical mentorship: help engineers grow in ASIC/driver-level expertise.</div>
</li>
<li style="color: black;">
<div style="color: black;">Define sprint goals and ensure timely delivery of features and bug fixes.</div>
</li>
<li style="color: black;">
<div style="color: black;">Act as the voice of the HAL team in architectural and planning discussions.</div>
</li>
</ul>
<div style="color: black;"><span class="normal bold" style="font-size: 0.8125rem; color: black; font-weight: bold;">What We&rsquo;re Looking For</span></div>
<ul>
<li style="color: black;">
<div style="color: black;">Strong background in C/Linux systems programming and networking protocols.</div>
</li>
<li style="color: black;">
<div style="color: black;">Experience leading engineering teams (formal management or tech lead capacity).</div>
</li>
<li style="color: black;">
<div style="color: black;">Familiarity with vendor SDKs and low-level hardware/software integration.</div>
</li>
<li style="color: black;">
<div style="color: black;">Strong communication skills: ability to bridge hardware, control plane, and QA.</div>
</li>
<li style="color: black;">
<div style="color: black;">Passion for mentoring and building high-performing teams.</div>
</li>
</ul>
<div style="color: black;"><span class="normal bold" style="font-size: 0.8125rem; color: black; font-weight: bold;">Career Opportunity</span></div>
<div style="color: black;">This is not a maintenance role &mdash; you&rsquo;ll <strong>lead the creation of a brand-new HAL layer</strong> for a greenfield NOS. You will grow into a <strong>key leadership position</strong> as our engineering organization scales from dozens to hundreds of engineers.</div>
</div>

<div style="color: black;">
<div style="color: black;"><span class="normal bold" style="font-size: 0.8125rem; color: black; font-weight: bold;">About the Role</span></div>
<div style="color: black;">As <strong>Team Lead of the Control Plane group</strong>, you&rsquo;ll guide a team of engineers building the NOS routing brain. This is a hybrid role: you&rsquo;ll still code and review protocol implementations, but you&rsquo;ll also mentor engineers, manage delivery, and shape the team&rsquo;s growth.</div>
<div style="color: black;">Your team will ensure that the NOS scales across data center fabrics, telco backbones, and multi-cloud environments.<br><br></div>
<div style="color: black;"><span class="normal bold" style="font-size: 0.8125rem; color: black; font-weight: bold;">What You&rsquo;ll Do</span></div>
<ul>
<li style="color: black;">
<div style="color: black;">Lead a team (5&ndash;10 engineers) developing control plane protocols (BGP, OSPF, IS-IS, LDP, MPLS, BFD, SNMP).</div>
</li>
<li style="color: black;">
<div style="color: black;">Review code, set engineering practices, and ensure protocol correctness and performance.</div>
</li>
<li style="color: black;">
<div style="color: black;">Coordinate with data plane, HAL, and management plane teams for seamless end-to-end integration.</div>
</li>
<li style="color: black;">
<div style="color: black;">Mentor engineers in protocol design, RFC interpretation, and debugging techniques.</div>
</li>
<li style="color: black;">
<div style="color: black;">Drive sprint planning and ensure timely, high-quality delivery.</div>
</li>
<li style="color: black;">
<div style="color: black;">Represent the control plane team in system-level architectural reviews.</div>
</li>
</ul>
<div style="color: black;"><span class="normal bold" style="font-size: 0.8125rem; color: black; font-weight: bold;">What We&rsquo;re Looking For</span></div>
<ul>
<li style="color: black;">
<div style="color: black;">Solid background in C/Linux networking software.</div>
</li>
<li style="color: black;">
<div style="color: black;">Experience leading or mentoring teams (formal lead or strong tech lead role).</div>
</li>
<li style="color: black;">
<div style="color: black;">Expertise in routing protocols and distributed systems design.</div>
</li>
<li style="color: black;">
<div style="color: black;">Strong communication and collaboration skills across hardware and software boundaries.</div>
</li>
<li style="color: black;">
<div style="color: black;">Passion for building teams and scaling engineering culture.</div>
</li>
</ul>
<div style="color: black;"><span class="normal bold" style="font-size: 0.8125rem; color: black; font-weight: bold;">Career Opportunity</span></div>
<div style="color: black;">This is your chance to <strong>build and lead the control plane team of a brand-new NOS</strong>. As our engineering organization grows, you&rsquo;ll evolve into a <strong>senior leadership role</strong>, guiding one of the most critical components of the system.</div>
</div>

<div style="color: black;">
<div style="color: black;"><span class="normal bold" style="font-size: 0.8125rem; color: black; font-weight: bold;">About the Role</span></div>
<div style="color: black;">Join our mission to build a <strong>next-generation Network Operating System (NOS)</strong> powering data center switches and routers worldwide. As part of the <strong>Control Plane Engineering team</strong>, you&rsquo;ll design and implement the brains of our networking stack &mdash; from dynamic routing protocols to system orchestration.</div>
<div style="color: black;">This is a rare chance to contribute to a <strong>greenfield NOS/NMS suite</strong>, working directly with ASIC-driven data planes while building scalable, reliable control plane software.<br><br></div>
<div style="color: black;"><span class="normal bold" style="font-size: 0.8125rem; color: black; font-weight: bold;">What You&rsquo;ll Do</span></div>
<ul>
<li style="color: black;">
<div style="color: black;">Design and develop the Control Plane of our NOS, implementing and extending protocols such as BGP, OSPF, IS-IS, LDP, BFD, STP, and SNMP.</div>
</li>
<li style="color: black;">
<div style="color: black;">Debug and optimize performance in complex multithreaded systems.</div>
</li>
<li style="color: black;">
<div style="color: black;">Collaborate closely with data plane engineers to ensure seamless integration of routing decisions into hardware forwarding.</div>
</li>
<li style="color: black;">
<div style="color: black;">Support QA in developing automated tests for protocol correctness and scalability.</div>
</li>
<li style="color: black;">
<div style="color: black;">Participate in code reviews, bringing best practices into a high-performance codebase.</div>
</li>
<li style="color: black;">
<div style="color: black;">Stay current with emerging standards and incorporate them into production software.</div>
</li>
</ul>
<div style="color: black;"><span class="normal bold" style="font-size: 0.8125rem; color: black; font-weight: bold;">What We&rsquo;re Looking For</span></div>
<ul>
<li style="color: black;">
<div style="color: black;">Degree (or equivalent experience) in CS, EE, or related field.</div>
</li>
<li style="color: black;">
<div style="color: black;">Strong C programming skills; experience in Linux system-level development.</div>
</li>
<li style="color: black;">
<div style="color: black;">Solid understanding of Ethernet/IP protocols and at least one dynamic routing protocol (BGP, OSPF).</div>
</li>
<li style="color: black;">
<div style="color: black;">Ability to interpret IETF RFCs/IEEE standards and implement compliant behavior in code.</div>
</li>
<li style="color: black;">
<div style="color: black;">Experience debugging multithreaded and large-scale software (&gt;3GB codebases).</div>
</li>
<li style="color: black;">
<div style="color: black;">Knowledge of Linux kernel networking internals.</div>
</li>
</ul>
<div style="color: black;"><span class="normal bold" style="font-size: 0.8125rem; color: black; font-weight: bold;">Ways to Stand Out</span></div>
<ul>
<li style="color: black;">
<div style="color: black;">Experience with open routing suites (FRR, Quagga).</div>
</li>
<li style="color: black;">
<div style="color: black;">Familiarity with Netlink, switchdev, and Linux device drivers.</div>
</li>
<li style="color: black;">
<div style="color: black;">Deep knowledge of MPLS (LDP, RSVP-TE).</div>
</li>
<li style="color: black;">
<div style="color: black;">Experience writing Linux daemons and multithreaded services.</div>
</li>
<li style="color: black;">
<div style="color: black;">Exposure to embedded systems and hardware integration.</div>
</li>
<li style="color: black;">
<div style="color: black;">Cloud/distributed systems background, including virtualization (KVM/QEMU, Docker, Kubernetes).</div>
</li>
<li style="color: black;">
<div style="color: black;">Strong Git flow/code review discipline (GitLab preferred).</div>
</li>
</ul>
</div>

<div style="color: black;">
<div style="color: black;"><span class="normal bold" style="font-size: 0.8125rem; color: black; font-weight: bold;">About the Role</span></div>
<div style="color: black;">As a Senior SDET, you&rsquo;ll <strong>architect and lead test automation</strong> for complex networking features, scaling frameworks to validate control plane, data plane, and hardware-software interactions. You&rsquo;ll drive best practices in test development and mentor junior SDETs.</div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;"><span class="normal bold" style="font-size: 0.8125rem; color: black; font-weight: bold;">What You&rsquo;ll Do</span></div>
<ul>
<li style="color: black;">
<div style="color: black;">Architect large-scale automated testing systems for data center and telco networking.</div>
</li>
<li style="color: black;">
<div style="color: black;">Design simulation environments reproducing customer topologies (BGP EVPN fabrics, MPLS backbones).</div>
</li>
<li style="color: black;">
<div style="color: black;">Lead CI/CD strategy for continuous, automated validation of NOS builds.</div>
</li>
<li style="color: black;">
<div style="color: black;">Build and extend advanced test suites using <strong>pytest, nose, or equivalent frameworks</strong>.</div>
</li>
<li style="color: black;">
<div style="color: black;">Mentor SDETs and QA engineers in coding and automation practices.</div>
</li>
<li style="color: black;">
<div style="color: black;">Partner with development leads to ensure test coverage aligns with feature roadmaps.</div>
</li>
</ul>
<div style="color: black;"><span class="normal bold" style="font-size: 0.8125rem; color: black; font-weight: bold;">What We&rsquo;re Looking For</span></div>
<ul>
<li style="color: black;">
<div style="color: black;">6+ years of experience in test automation, preferably in networking or systems.</div>
</li>
<li style="color: black;">
<div style="color: black;">Strong expertise in Python and Bash; capable of building 10k+ LOC frameworks.</div>
</li>
<li style="color: black;">
<div style="color: black;">Proven experience in <strong>test automation frameworks (pytest/nose)</strong> and scaling them.</div>
</li>
<li style="color: black;">
<div style="color: black;">Deep knowledge of data center networking protocols (BGP, EVPN, MPLS).</div>
</li>
<li style="color: black;">
<div style="color: black;">Experience with Jenkins, Ansible, and Git-based workflows.</div>
</li>
</ul>
<div style="color: black;">&nbsp;</div>
</div>

<div style="color: black;">
<div style="color: black;"><strong>Location:</strong> Dubai - UAE</div>
<div style="color: black;"><strong>Team:</strong> SoC Architecture &ndash; NPU Core &amp; ISA</div>
<div style="color: black;"><strong>Type:</strong> Full-time &ndash; On-site</div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;"><span class="normal bold" style="font-size: 0.8125rem; color: black; font-weight: bold;"><strong>About Us</strong></span></div>
<div style="color: black;">We are a tech company specializing in the design and development of cutting-edge, customized server hardware solutions optimized for artificial intelligence and machine learning applications.</div>
<div style="color: black;">Our mission is to empower businesses and researchers to accelerate their AI initiatives by providing them with high-performance, scalable, and energy-efficient hardware infrastructure.</div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;">As a rapidly growing company at the forefront of AI hardware innovation, we are constantly seeking talented and motivated individuals to join our team. We offer a dynamic and challenging work environment with opportunities to make a significant impact on the future of AI.</div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;"><span class="normal bold" style="font-size: 0.8125rem; color: black; font-weight: bold;"><strong>Your Mission</strong></span></div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;">As a <strong>RISC-V Architect</strong>, you will own the architecture of our AI Accelerator &mdash; a many-core RISC-V compute cluster. You will define the base ISA, the vector and matrix extensions, the per-core microarchitecture, and the cluster/NoC topology that turn real AI training and inference workloads into synthesizable, verification-ready RTL feeding our next-generation silicon. You set the architectural contracts that RTL, verification, toolchain, and compiler teams build against, and drive the integration and microarchitecture reviews that keep silicon faithful to the spec.</div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;"><span class="normal bold" style="font-size: 0.8125rem; color: black; font-weight: bold;"><strong>Responsibilities</strong></span></div>
<ul>
<li style="color: black;">
<div style="color: black;"><strong>RISC-V core and ISA definition:</strong> define the base ISA, privilege modes, and scalar pipeline scope; specify the microarchitecture requirements that balance programmability, performance, and PPA.</div>
</li>
<li style="color: black;">
<div style="color: black;"><strong>Vector and matrix extension architecture:</strong> own the RVV and AME matrix extensions &mdash; its register and accumulator model, instruction encodings in the custom-opcode space, and the golden-model semantics that define correct behavior.</div>
</li>
<li style="color: black;">
<div style="color: black;"><strong>NoC and cluster architecture:</strong> design the on-chip interconnect &mdash; mesh topology, routing, flow control, virtual channels, the DMA/data-movement model, and how the cluster is represented to system software and the compiler.</div>
</li>
<li style="color: black;">
<div style="color: black;"><strong>Memory and data-movement co-design:</strong> architect the per-core SRAM/scratchpad, DMA engines, and end-to-end data flows between local memory, the NoC, and the compute cores datapaths to sustain persistent throughput.</div>
</li>
<li style="color: black;">
<div style="color: black;"><strong>Golden model and specification ownership:</strong> produce microarchitecture and AME specifications and interface contracts, and own the golden reference model's behavior, providing RTL, DV, and toolchain teams with one authoritative reference to build and verify against.</div>
</li>
<li style="color: black;">
<div style="color: black;"><strong>Compiler and toolchain contracts:</strong> define the ISA/ABI and the intrinsic/builtin surface that the compiler backend and AME code generation target, collaborating with the toolchain team on autovectorization, tiling, and code-generation assumptions.</div>
</li>
<li style="color: black;">
<div style="color: black;"><strong>Hands-on microarchitecture and integration:</strong> prototype and pressure-test critical blocks in SystemVerilog, and drive the integration and microarchitecture reviews across RTL, verification, compiler, performance, and physical-design teams to keep implementation faithful to the spec from ISA definition through to taped-out IP.</div>
</li>
</ul>
<div style="color: black;"><span class="normal bold" style="font-size: 0.8125rem; color: black; font-weight: bold;"><strong>Requirements</strong></span></div>
<ul>
<li style="color: black;">
<div style="color: black;">Bachelor's or Master's in Computer Engineering, Electrical Engineering, Computer Science, or related field.</div>
</li>
<li style="color: black;">
<div style="color: black;">10+ years in CPU, DSP, or NPU/accelerator IP architecture, with a proven track record of taking compute-core IP from ISA definition through RTL to silicon.</div>
</li>
<li style="color: black;">
<div style="color: black;">Deep expertise in the RISC-V architecture &mdash; the base ISA, privilege modes, and the practice of defining and extending ISAs with custom, non-standard instructions.</div>
</li>
<li style="color: black;">
<div style="color: black;">Hands-on experience with the RISC-V Vector extension (RVV) or matrix/tensor extensions (AME or equivalent AI matrix engines), including register models, instruction encodings, and datapath implications.</div>
</li>
<li style="color: black;">
<div style="color: black;">Strong grasp of NoC/interconnect architecture &mdash; mesh/torus topologies, routing, flow control, and virtual channels &mdash; with a clear feel for the latency, bandwidth, and area trade-offs of an implementation.</div>
</li>
<li style="color: black;">
<div style="color: black;">Solid microarchitecture skills: pipelines, memory hierarchy, DMA, coherency and memory ordering, and hazard handling, with the ability to reason quantitatively about PPA.</div>
</li>
<li style="color: black;">
<div style="color: black;">Solid understanding of AI workloads (GEMM, conv-as-GEMM, attention) and how they stress compute, memory, and interconnect.</div>
</li>
<li style="color: black;">
<div style="color: black;">Hands-on SystemVerilog experience &mdash; writing and reviewing synthesizable RTL and testbenches, co-simulating against a golden reference model, and driving coverage closure.</div>
</li>
<li style="color: black;">
<div style="color: black;">Proficiency in C/C++ and scripting (Python, Bash); comfort with instruction-set simulators, profilers, and performance modeling across the HW/SW boundary.</div>
</li>
<li style="color: black;">
<div style="color: black;">Excellent cross-functional communication and documentation skills; ability to write precise specifications and drive integration and microarchitecture reviews to architectural alignment with internal and external partners.</div>
</li>
</ul>
<div style="color: black;"><span class="normal bold" style="font-size: 0.8125rem; color: black; font-weight: bold;"><strong>Preferred Qualifications (Nice-to-Haves)</strong></span></div>
<ul>
<li style="color: black;">
<div style="color: black;">Direct experience with the RVV 1.0 and the emerging RISC-V Matrix (AMEX/IME) draft specifications, or active participation in a RISC-V working group.</div>
</li>
<li style="color: black;">
<div style="color: black;">Experience with a taped-out RISC-V core or contributions to open-hardware silicon.</div>
</li>
<li style="color: black;">
<div style="color: black;">Familiarity with MLIR/LLVM compiler stacks and graph-compilation flows (tiling, fusion, layout, quantization) for AI accelerators.</div>
</li>
<li style="color: black;">
<div style="color: black;">Hands-on with open-source RISC-V verification tooling (riscv-arch-test, riscv-dv, cocotb, Verilator) and formal methods.</div>
</li>
<li style="color: black;">
<div style="color: black;">Knowledge of chiplet/multi-die integration and NoC-to-AXI/CHI fabric bridging.</div>
</li>
<li style="color: black;">
<div style="color: black;">Experience with power/performance modeling and correlating pre-silicon models to silicon behavior.</div>
</li>
</ul>
<div style="color: black;"><span class="normal bold" style="font-size: 0.8125rem; color: black; font-weight: bold;"><strong>Why Join Us</strong></span></div>
<ul>
<li style="color: black;">
<div style="color: black;">Own the architecture of a fully proprietary AI accelerator core &mdash; your ISA and microarchitecture decisions define silicon that we ship, not a derivative of someone else's IP.</div>
</li>
<li style="color: black;">
<div style="color: black;">Work at the frontier of RISC-V for AI: extend RVV and define a custom matrix engine on a fully open-source toolchain, alongside RTL, verification, compiler, and physical-design teams.</div>
</li>
<li style="color: black;">
<div style="color: black;">Build the compute foundation that feeds our next-generation accelerator tapeout, with hands-on impact from spec to silicon.</div>
</li>
<li style="color: black;">
<div style="color: black;">Competitive compensation, growth opportunities, and the chance to help define the platform that powers advanced AI workloads.</div>
</li>
</ul>
<div style="color: black;"><span class="normal bold" style="font-size: 0.8125rem; color: black; font-weight: bold;"><strong>Ready to Accelerate the Future of AI?</strong></span></div>
<div style="color: black;">If you're passionate about architecting AI acceleration cores from the ISA up &mdash; turning AI workloads into custom vector and matrix silicon &mdash; we'd love to hear from you.</div>
<div style="color: black;">Apply now and help us deliver production</div>
</div>

<div style="color: black;">
<div style="color: black;"><strong><span class="large" style="font-size: 1.125rem; color: black;">Your Mission</span></strong></div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;">Own the end-to-end <strong>verification</strong> of critical ASIC subsystems&mdash;from compute pipelines and high-speed I/O to interconnects and multi-die coherency. You&rsquo;ll architect UVM environments and golden reference models, turn specs into assertions and checkers, drive coverage to closure, and tie in emulation/FPGA and SW-in-the-loop to catch bugs before tape-out. This is where one missed corner case can cost millions&mdash;finding it early keeps our AI silicon on schedule and on target.</div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;"><span class="large" style="font-size: 1.125rem; color: black;"><strong>Responsibilities</strong></span></div>
<ul>
<li style="color: black;">
<div style="color: black;"><strong>Own block-to-subsystem verification</strong>: author verification plans from specs, define stimulus/coverage strategy, and deliver sign-off with data (functional/code/assertion coverage).</div>
</li>
<li style="color: black;">
<div style="color: black;"><strong>Build scalable UVM environments</strong>: agents, monitors, scoreboards, sequences, reference models (C++/Python/DPI), protocol checkers, and reusable components.</div>
</li>
<li style="color: black;">
<div style="color: black;"><strong>Exercise real workloads</strong>: co-sim with firmware/drivers, run emulation/FPGA prototypes, and correlate performance/behavior with architectural models.</div>
</li>
<li style="color: black;">
<div style="color: black;"><strong>Apply assertions &amp; formal</strong>: write SVA, run formal where appropriate (protocol/liveness/safety), and integrate results into overall coverage.</div>
</li>
<li style="color: black;">
<div style="color: black;"><strong>Close quality gates</strong>: lint/CDC/RDC verification collaboration, gate-level/reset/power-up scenarios, low-power (UPF) intent checks.</div>
</li>
<li style="color: black;">
<div style="color: black;"><strong>Harden regressions</strong>: own CI pipelines, randomized/constrained tests, triage failures, root-cause with RTL/design, and track fixes to closure.</div>
</li>
<li style="color: black;">
<div style="color: black;"><strong>Interface &amp; document</strong>: keep specs, test plans, coverage dashboards, and bug reports clear for Architects, RTL, Firmware/Drivers, and DFT/PD teams.</div>
</li>
</ul>
<div style="color: black;"><span class="large" style="font-size: 1.125rem; color: black;"><strong>You'll Collaborate With</strong></span></div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;">Silicon architects (clarifying intent and performance targets), RTL designers (debug and ECOs), firmware and Linux driver teams (HW/SW co-verification), performance architects (workload traces and counters), and EDA/CAD (flows, regressions, metrics) to ensure first-pass silicon success.</div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;"><strong><span class="large" style="font-size: 1.125rem; color: black;">Minimum Qualifications</span></strong></div>
<ul>
<li style="color: black;">
<div style="color: black;">7+ years in ASIC/SoC verification with <strong>SystemVerilog/UVM</strong> (ownership from test plan to sign-off).</div>
</li>
<li style="color: black;">
<div style="color: black;">Strong command of <strong>constrained-random stimulus</strong>, <strong>scoreboarding</strong>, <strong>coverage-driven</strong> verification, and <strong>SVA</strong>.</div>
</li>
<li style="color: black;">
<div style="color: black;">Hands-on with major simulators (e.g., VCS/Questa/Xcelium) and regression/CI tooling.</div>
</li>
<li style="color: black;">
<div style="color: black;">Familiarity with standard protocols (AMBA, AXI, APB, AHB) and industrial VIPs</div>
</li>
<li style="color: black;">
<div style="color: black;">Experience verifying complex IP/subsystems (at least one of: multi-core compute, NoC/coherency, high-speed I/O like PCIe, Ethernet 100/400G, HBM/DDR, UCIe).</div>
</li>
<li style="color: black;">
<div style="color: black;">Proficient in scripting for automation (Python/TCL/Make) and building reusable verification components.</div>
</li>
<li style="color: black;">
<div style="color: black;">Solid understanding of SoC fundamentals: resets, clocking, CDC/RDC, back-pressure/flow control, performance counters.</div>
</li>
</ul>
<div style="color: black;"><strong><span class="large" style="font-size: 1.125rem; color: black;">Preferred (Nice-to-Haves)</span></strong></div>
<ul>
<li style="color: black;">
<div style="color: black;">Emulation/FPGA prototyping (Palladium/Zebu/Veloce; Xilinx/Intel) and SW-in-the-loop setups.</div>
</li>
<li style="color: black;">
<div style="color: black;">Formal verification experience (JasperGold/VC Formal) and assertion methodology leadership.</div>
</li>
<li style="color: black;">
<div style="color: black;">DFT/DFD awareness and post-silicon bring-up experience.</div>
</li>
<li style="color: black;">
<div style="color: black;">Exposure to AI accelerator domains (systolic/dataflow, memory hierarchies, tiling) and traffic modeling.</div>
</li>
<li style="color: black;">
<div style="color: black;">Experience building coverage dashboards and integrating verification metrics into CI/CD.</div>
</li>
<li style="color: black;">
<div style="color: black;">Experience with C/C++/DPI for RTL Co-Simulation.</div>
</li>
</ul>
<div style="color: black;">&nbsp;</div>
</div>

Athens Office

<div style="color: black;">
<div style="color: black;"><strong>Location:</strong> Dubai - UAE</div>
<div style="color: black;"><strong>Team:</strong> SoC Physical Design Team</div>
<div style="color: black;"><strong>Type:</strong> Full-time &ndash; On-site</div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;">About Us</div>
<div style="color: black;">We&nbsp;design and develop&nbsp;customized server hardware solutions optimized for artificial intelligence and machine learning workloads. Our focus is on high-performance, scalable, and energy-efficient infrastructure for next-generation AI compute.</div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;">Role Overview</div>
<div style="color: black;">Evollabs Tech is hiring a <strong>Senior DFT Engineer</strong> to own design-for-test architecture, implementation, verification, and silicon bring-up for advanced AI SoC / ASIC accelerator designs.</div>
<div style="color: black;">This role will work across RTL, verification, physical design, product engineering, ATE, and external partners to deliver testable, diagnosable, production-ready silicon.</div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;">Responsibilities</div>
<ul>
<li style="color: black;">
<div style="color: black;">Define and implement DFT architectures for complex AI SoC/ASIC blocks and subsystems.</div>
</li>
<li style="color: black;">
<div style="color: black;">Own scan insertion, scan compression, ATPG, fault coverage closure, and DFT signoff.</div>
</li>
<li style="color: black;">
<div style="color: black;">Implement and support MBIST, LBIST, JTAG, boundary scan, test access, and memory repair features.</div>
</li>
<li style="color: black;">
<div style="color: black;">Develop DFT specifications, test plans, coverage targets, constraints, and signoff criteria.</div>
</li>
<li style="color: black;">
<div style="color: black;">Work with RTL and verification teams to ensure DFT requirements are built into the design early.</div>
</li>
<li style="color: black;">
<div style="color: black;">Collaborate with physical design teams on scan reordering, test-mode timing, congestion, ECOs, and implementation closure.</div>
</li>
<li style="color: black;">
<div style="color: black;">Debug DFT issues across RTL, gate-level simulation, synthesis, STA, ATPG, physical implementation, and silicon bring-up.</div>
</li>
<li style="color: black;">
<div style="color: black;">Support ATE pattern delivery, silicon debug, diagnostics, yield learning, and production test ramp.</div>
</li>
<li style="color: black;">
<div style="color: black;">Communicate DFT status, risks, trade-offs, and signoff readiness clearly with internal teams, external partners, vendors, and stakeholders.</div>
</li>
<li style="color: black;">
<div style="color: black;">Build scripts and automation to improve DFT implementation, reporting, pattern generation, and debug</div>
</li>
</ul>
<div style="color: black;">Minimum Qualifications (Must Have)</div>
<ul>
<li style="color: black;">
<div style="color: black;">7+ years of hands-on DFT experience in ASIC or SoC development.</div>
</li>
<li style="color: black;">
<div style="color: black;">Strong experience with scan insertion, ATPG, scan compression, fault simulation, and coverage closure.</div>
</li>
<li style="color: black;">
<div style="color: black;">Experience with MBIST, LBIST, JTAG, boundary scan, and test access architecture.</div>
</li>
<li style="color: black;">
<div style="color: black;">Strong understanding of scan shift/capture timing, at-speed testing, test-mode constraints, and multi-clock-domain DFT.</div>
</li>
<li style="color: black;">
<div style="color: black;">Experience debugging DFT issues across RTL, gate-level simulation, synthesis, STA, ATPG, and silicon bring-up.</div>
</li>
<li style="color: black;">
<div style="color: black;">Experience with complex SoC/IP integration, such as NoC, CPU, GPU/NPU, PCIe, Ethernet, UCIe, HBM/GDDR, or other high-speed interfaces.</div>
</li>
<li style="color: black;">
<div style="color: black;">Proficiency with industry-standard DFT tools such as Siemens Tessent, Synopsys TestMAX/DFT Compiler, Cadence Modus, or equivalent.</div>
</li>
<li style="color: black;">
<div style="color: black;">Strong scripting skills in Tcl, Python, Perl, or shell.</div>
</li>
<li style="color: black;">
<div style="color: black;">Excellent written and verbal communication skills, including the ability to work effectively with internal engineering teams, external partners, vendors, and cross-functional stakeholders.</div>
</li>
</ul>
<div style="color: black;"><strong>Preferred Qualifications (Nice to Have)</strong></div>
<ul>
<li style="color: black;">
<div style="color: black;">Experience with AI accelerators, GPUs, NPUs, or highly parallel compute SoCs.</div>
</li>
<li style="color: black;">
<div style="color: black;">Experience with advanced-node, high-frequency, or high-density designs.</div>
</li>
<li style="color: black;">
<div style="color: black;">Experience with chiplets, multi-die systems, UCIe, 2.5D packaging, or package-aware test strategies.</div>
</li>
<li style="color: black;">
<div style="color: black;">Experience with HBM/GDDR or other high-bandwidth memory subsystem test requirements.</div>
</li>
<li style="color: black;">
<div style="color: black;">Experience with low-power DFT, UPF-aware test implementation, power domains, and power-aware ATPG.</div>
</li>
<li style="color: black;">
<div style="color: black;">Experience with silicon bring-up, ATE debug, diagnostics, yield ramp, and production test optimization.</div>
</li>
<li style="color: black;">
<div style="color: black;">Prior tapeout experience on advanced-node SoCs.</div>
</li>
</ul>
<div style="color: black;">What Success Really Means</div>
<ul>
<li style="color: black;">
<div style="color: black;">First silicon is testable, diagnosable, and ready for bring-up without major DFT workarounds.</div>
</li>
<li style="color: black;">
<div style="color: black;">DFT coverage targets are met across logic, memory, scan, and relevant fault models.</div>
</li>
<li style="color: black;">
<div style="color: black;">Test patterns are delivered on time with acceptable runtime, power, and ATE compatibility.</div>
</li>
<li style="color: black;">
<div style="color: black;">Physical design, timing, and manufacturing teams can close signoff without DFT-driven schedule risk.</div>
</li>
<li style="color: black;">
<div style="color: black;">Silicon debug and yield learning are accelerated through strong diagnostics and clear test visibility.</div>
</li>
</ul>
<div style="color: black;">&nbsp;</div>
<div style="color: black;"><strong>Ready to accelerate the future of AI?</strong></div>
<div style="color: black;">Submit your application and show us how you think systematically about DFT architecture, coverage closure, silicon debug, and building testable silicon that scales.</div>
<div style="color: black;"><em style="color: black;">Join us in our mission to democratize AI compute &mdash; where your DFT expertise helps turn advanced AI silicon into reliable, production-ready infrastructure.</em></div>
</div>

<div style="color: black;">
<div style="color: black;"><span class="large bold" style="font-size: 1.125rem; color: black; font-weight: bold;">About Us</span></div>
<div style="color: black;">We are a tech company specializing in the design and development of cutting-edge, customized server hardware solutions optimized for artificial intelligence and machine learning applications. Our mission is to empower businesses and researchers to accelerate their AI initiatives by providing them with high-performance, scalable, and energy-efficient hardware infrastructure.</div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;">As a rapidly growing company at the forefront of AI hardware innovation, we are constantly seeking talented and motivated individuals to join our team. We offer a dynamic and challenging work environment, with opportunities to make a significant impact on the future of AI technology.</div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;"><span class="large bold" style="font-size: 1.125rem; color: black; font-weight: bold;">You'll Collaborate With</span></div>
<div style="color: black;">Compiler engineers, firmware &amp; driver engineers, hardware architects, ML framework engineers and performance &amp; validation teams</div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;"><span class="large bold" style="font-size: 1.125rem; color: black; font-weight: bold;">What You'll Own</span></div>
<ul>
<li style="color: black;">
<div style="color: black;">The core runtime architecture that bridges the compiler and the hardware</div>
</li>
<li style="color: black;">
<div style="color: black;">Runtime execution engine performance and stability</div>
</li>
<li style="color: black;">
<div style="color: black;">Device memory management design and efficiency</div>
</li>
<li style="color: black;">
<div style="color: black;">Command submission and hardware interaction layer (in collaboration with firmware/driver teams)</div>
</li>
<li style="color: black;">
<div style="color: black;">Concurrency and scheduling model for model execution</div>
</li>
<li style="color: black;">
<div style="color: black;">Observability tooling (profiling, logging, tracing) within the runtime</div>
</li>
<li style="color: black;">
<div style="color: black;">Technical design decisions that ensure long-term scalability and maintainability</div>
</li>
</ul>
<div style="color: black;"><span class="large bold" style="font-size: 1.125rem; color: black; font-weight: bold;">Minimum Qualifications</span></div>
<ul>
<li style="color: black;">
<div style="color: black;">5&ndash;8+ years of experience in systems software, runtime systems, or performance-critical infrastructure</div>
</li>
<li style="color: black;">
<div style="color: black;">Strong proficiency in <strong>C/C++</strong>and Python</div>
</li>
<li style="color: black;">
<div style="color: black;">Solid understanding of fundamentals of operating systems, multi-threading, synchronization, memory management, and cache behavior</div>
</li>
<li style="color: black;">
<div style="color: black;">Experience working close to hardware (GPU, accelerator, driver, or firmware environments)</div>
</li>
<li style="color: black;">
<div style="color: black;">Familiarity with command queues, execution engines, and DMA-based systems</div>
</li>
<li style="color: black;">
<div style="color: black;">Understanding of computational graphs, tensor execution, and memory layouts</div>
</li>
<li style="color: black;">
<div style="color: black;">Experience profiling and optimizing latency and throughput in performance-sensitive systems</div>
</li>
</ul>
<div style="color: black;"><span class="large bold" style="font-size: 1.125rem; color: black; font-weight: bold;">Preferred Qualifications</span></div>
<ul>
<li style="color: black;">
<div style="color: black;">Experience building or architecting a runtime from scratch</div>
</li>
<li style="color: black;">
<div style="color: black;">Familiarity with MLIR, LLVM, or compiler-runtime interfaces</div>
</li>
<li style="color: black;">
<div style="color: black;">Experience with one or many from CUDA, ROCm, TensorRT, TVM, XLA, ONNX Runtime or similar runtimes</div>
</li>
<li style="color: black;">
<div style="color: black;">Experience integrating custom hardware backends into PyTorch, ONNX or OpenXLA</div>
</li>
<li style="color: black;">
<div style="color: black;">Knowledge of quantization and mixed-precision inference</div>
</li>
<li style="color: black;">
<div style="color: black;">Experience with multi-device or distributed execution</div>
</li>
<li style="color: black;">
<div style="color: black;">Background in AI accelerator or semiconductor environments</div>
</li>
</ul>
<div style="color: black;"><span class="large bold" style="font-size: 1.125rem; color: black; font-weight: bold;">What Success Looks Like</span></div>
<ul>
<li style="color: black;">
<div style="color: black;">You enable reliable end-to-end execution of compiled models on our NPU</div>
</li>
<li style="color: black;">
<div style="color: black;">Runtime overhead is minimal and performance targets are consistently met</div>
</li>
<li style="color: black;">
<div style="color: black;">Memory management and scheduling are efficient and scalable</div>
</li>
<li style="color: black;">
<div style="color: black;">The runtime architecture is robust, maintainable, and extensible</div>
</li>
<li style="color: black;">
<div style="color: black;">Compiler, firmware, and hardware teams can build confidently on top of your execution layer</div>
</li>
<li style="color: black;">
<div style="color: black;">The system supports real-world AI workloads with stability and observability</div>
</li>
</ul>
<div style="color: black;"><em style="color: black;">Join us in our mission to democratize AI compute &mdash; where your firmware expertise becomes the bedrock of tomorrow's AI breakthroughs.</em></div>
</div>

<div style="color: black;">
<div style="color: black;">Location: Dubai - UAE</div>
<div style="color: black;">Team: Hardware Engineering &ndash; Board Design &amp; Bring-Up</div>
<div style="color: black;">Type: Full-time &ndash; On-site<br><br></div>
<div style="color: black;"><strong>About Us<br></strong></div>
<div style="color: black;">We are a tech company specializing in the design and development of cutting-edge, customized&nbsp;server hardware solutions optimized for artificial intelligence and machine learning applications.&nbsp;Our mission is to empower businesses and researchers to accelerate their AI initiatives by&nbsp;providing them with high-performance, scalable, and energy-efficient hardware infrastructure.</div>
<div style="color: black;">As a rapidly growing company at the forefront of AI hardware innovation, we are constantly&nbsp;seeking talented and motivated individuals to join our team. We offer a dynamic and challenging&nbsp;work environment, with opportunities to make a significant impact on the future of AI technology.<br><br></div>
<div style="color: black;"><strong>Your Mission</strong></div>
<div style="color: black;">As a Staff Hardware Board Design Engineer, you will be the electrical design authority for the&nbsp;boards that carry our AI accelerator silicon, from the first test PCB that powers up a new chip to&nbsp;the production accelerator card or module that ships in a data center rack. You will set board-level architecture, translate silicon and system requirements into schematics, power trees, and&nbsp;high-speed interface budgets, define the constraints that drive layout, and take the resulting&nbsp;hardware through lab bring-up, characterization, and debug. You will own board programs end&nbsp;to end and be the person the silicon, firmware, and validation teams come to when the platform&nbsp;has to work.<br><br></div>
<div style="color: black;"><strong>Responsibilities</strong></div>
<div style="color: black;">&bull; Accelerator board architecture and schematic design: set board-level architecture&nbsp;and own schematic capture for AI accelerator cards, modules, and system boards,&nbsp;including component selection, clocking and reset topologies, sideband management&nbsp;interfaces, and connector and form-factor decisions.</div>
<div style="color: black;">&bull; Test PCB design for silicon bring-up: design the evaluation, characterization, and&nbsp;socketed test boards used to power up and qualify new chips, providing programmable&nbsp;rails and current sensing, clean clock sources, JTAG and scan access, probe and&nbsp;instrumentation points, thermal fixturing, and package breakout structures that make first&nbsp;silicon observable and debuggable.</div>
<div style="color: black;">&bull; Power delivery network design: design high-current, multi-rail power trees for&nbsp;accelerator-class devices, covering multi-phase VRM selection and compensation, PDN&nbsp;impedance targets, decoupling strategy, power sequencing and telemetry over PMBus,&nbsp;and protection and hot-swap behaviour.&bull; High-speed interface budgets and layout direction: define stackup, material,&nbsp;impedance, and routing constraints for PCIe Gen5 and Gen6, DDR5, LPDDR5, GDDR6&nbsp;and GDDR7 or HBM-adjacent interfaces, 100G to 800G Ethernet, and die-to-die and&nbsp;SerDes links, then drive layout execution with our in-house PCB layout and signal and&nbsp;power integrity engineers as well as external layout partners.</div>
<div style="color: black;">&bull; Lab bring-up, characterization, and debug: plan and execute board and silicon bring-&nbsp;up, run electrical characterization and margining, and root-cause failures across the&nbsp;hardware, firmware, and silicon boundary using oscilloscopes, high-bandwidth probes,&nbsp;BERTs, VNAs, protocol and power analyzers, and thermal imaging.</div>
<div style="color: black;">&bull; Manufacturing readiness and vendor execution: drive DFM, DFT, and DFA reviews,&nbsp;prototype and NPI builds, ECO and BOM management, and compliance activities with&nbsp;fabricators, assembly houses, ODMs, and contract manufacturers through to volume&nbsp;production.</div>
<div style="color: black;">&bull; Technical leadership and documentation: write board specifications, schematic&nbsp;review packages, bring-up and test plans, and errata, act as design authority in reviews,&nbsp;align silicon, package, firmware, thermal, mechanical, and validation teams around a&nbsp;single platform definition, and mentor engineers as the board team grows.<br><br></div>
<div style="color: black;"><strong>Requirements</strong></div>
<div style="color: black;">&bull; Bachelor&rsquo;s or Master&rsquo;s in Electrical Engineering, Electronics Engineering, or related field.</div>
<div style="color: black;">&bull; 10+ years of board-level hardware design experience with a strong focus on high-speed&nbsp;digital boards for compute, networking, or accelerator products, including at least one&nbsp;platform owned end to end from concept through volume production and at least one&nbsp;first-silicon bring-up.</div>
<div style="color: black;">&bull; Proven ownership of schematic capture and board architecture in a professional ECAD&nbsp;flow such as Cadence Allegro System Capture, OrCAD Capture, or Altium Designer.</div>
<div style="color: black;">&bull; Hands-on experience designing and debugging high-speed interfaces such as PCIe&nbsp;Gen4 or newer, DDR4 or DDR5, LPDDR, GDDR, or multi-gigabit SerDes and Ethernet&nbsp;links, including how loss, crosstalk, and return-path decisions shape the schematic and&nbsp;stackup.</div>
<div style="color: black;">&bull; Strong power electronics competence at board level: multi-phase VRM design, high-&nbsp;current PDN design, decoupling and target impedance analysis, power sequencing, and&nbsp;telemetry.</div>
<div style="color: black;">&bull; Demonstrated silicon or board bring-up experience: taking untested hardware from first&nbsp;power-on to functional and characterized, and driving issues to root cause.</div>
<div style="color: black;">&bull; Fluency with lab instrumentation and measurement practice, including oscilloscopes and&nbsp;probing technique, power and network analyzers, and protocol or bus analyzers.</div>
<div style="color: black;">&bull; Working knowledge of low-speed management and control subsystems: I2C, SMBus,&nbsp;SPI, UART, JTAG, EEPROM and FRU handling, BMC or MCU based board&nbsp;management, and reset and sequencing logic.</div>
<div style="color: black;">&bull; Practical command of DFM, DFT, and DFA, PCB fabrication and assembly processes,&nbsp;and design release packages, with experience working directly with fab and assembly&nbsp;vendors.<br>&bull; Proficiency with Python or equivalent scripting for lab automation, data capture, and&nbsp;measurement post-processing.</div>
<div style="color: black;">&bull; Demonstrated technical leadership: acting as design authority in schematic and layout&nbsp;reviews, steering external layout houses, ODMs, and component vendors, and&nbsp;mentoring less experienced engineers.</div>
<div style="color: black;">&bull; Excellent cross-functional communication and documentation skills, with the ability to&nbsp;lead design reviews and to drive alignment with silicon, firmware, mechanical, and&nbsp;manufacturing partners.<br><br></div>
<div style="color: black;"><strong>Preferred Qualifications (Nice-to-Haves)</strong></div>
<div style="color: black;">&bull; Experience with AI accelerator or GPU form factors such as OAM and UBB, SXM, PCIe&nbsp;CEM cards, or OCP and DC-MHS compliant platforms, including liquid-cooled designs.</div>
<div style="color: black;">&bull; Signal and power integrity simulation experience with tools such as Cadence Sigrity,&nbsp;Ansys HFSS or SIwave, Keysight ADS, or HyperLynx, and the ability to interpret and act&nbsp;on extraction results.</div>
<div style="color: black;">&bull; Silicon and package co-design exposure: BGA escape planning, substrate and 2.5D or&nbsp;HBM package constraints, and joint debug with package and ASIC teams.</div>
<div style="color: black;">&bull; Post-silicon characterization experience including voltage and frequency margining and&nbsp;correlating lab measurements with ATE or emulation results.</div>
<div style="color: black;">&bull; Familiarity with FPGA prototyping platforms, socketed test boards, and interposer or&nbsp;riser based debug hardware.</div>
<div style="color: black;">&bull; Experience with thermal and mechanical co-design for high-power boards, including cold&nbsp;plates, heatsink loading, and board stiffening.<br><br></div>
<div style="color: black;"><strong>Why Join Us</strong></div>
<div style="color: black;">&bull; Own the physical platform that our AI silicon runs on, where your board decisions&nbsp;directly determine whether the chip meets its performance, power, and reliability targets.</div>
<div style="color: black;">&bull; Work shoulder to shoulder with silicon, package, firmware, and validation engineers in a&nbsp;fast-moving team that values hands-on depth and measurement over guesswork.</div>
<div style="color: black;">&bull; Build hardware end to end, from the first bring-up fixture on a lab bench to a production&nbsp;accelerator platform, with real authority over architecture, vendor, and technology&nbsp;choices, and the scope to shape the board team as it grows.</div>
<div style="color: black;">&bull; Competitive compensation, growth opportunities, and the chance to help define the&nbsp;platform that powers advanced AI workloads.<br><br></div>
<div style="color: black;"><strong>Ready to Accelerate the Future of AI?</strong></div>
<div style="color: black;">If you&rsquo;re passionate about turning new silicon into working, measurable, manufacturable</div>
<div style="color: black;">hardware &mdash; we&rsquo;d love to hear from you.</div>
<div style="color: black;">Apply now and help us deliver production-ready platforms that make AI faster, safer, and more</div>
<div style="color: black;">efficient.</div>
</div>

<div style="color: black;">
<div style="color: black;">Location: Dubai - UAE</div>
<div style="color: black;">Team: Hardware Engineering &ndash; PCB Layout &amp; Signal Integrity</div>
<div style="color: black;">Type: Full-time &ndash; On-site<br><br></div>
<div style="color: black;"><strong>About Us</strong></div>
<div style="color: black;">We are a tech company specializing in the design and development of cutting-edge, customized&nbsp;server hardware solutions optimized for artificial intelligence and machine learning applications.&nbsp;Our mission is to empower businesses and researchers to accelerate their AI initiatives by&nbsp;providing them with high-performance, scalable, and energy-efficient hardware infrastructure.&nbsp;As a rapidly growing company at the forefront of AI hardware innovation, we are constantly&nbsp;seeking talented and motivated individuals to join our team. We offer a dynamic and challenging&nbsp;work environment, with opportunities to make a significant impact on the future of AI technology.<br><br></div>
<div style="color: black;"><strong>Your Mission</strong></div>
<div style="color: black;">As a High-Speed PCB Layout Engineer, you will own the physical realization of our AI&nbsp;accelerator boards: the stackups, the escape routing out of large fine-pitch ASIC packages, the&nbsp;multi-gigabit channels, and the high-current power shapes that decide whether a design closes&nbsp;its loss and impedance budgets. You will work from schematics and constraint sets owned by&nbsp;our board design engineers and turn them into dense, manufacturable, high layer count PCBs,&nbsp;spanning both production accelerator platforms and the test boards used for silicon bring-up and&nbsp;characterization.<br><br></div>
<div style="color: black;"><strong>Responsibilities</strong></div>
<div style="color: black;">&bull; High-density board layout ownership: own multi-layer PCB layouts end to end for AI&nbsp;accelerator cards, modules, system boards, and silicon test fixtures, from floorplanning&nbsp;and placement through routing, copper pour, and release.</div>
<div style="color: black;">&bull; ASIC package escape and high-speed routing: execute escape routing for large, fine-&nbsp;pitch BGA and route multi-gigabit channels including PCIe Gen6, GDDR7, and&nbsp;400G/800G Ethernet links, applying HDI, via-in pad and VIPPO, blind and buried vias,&nbsp;backdrilling, and any-layer interconnect where needed.</div>
<div style="color: black;">&bull; Stackup, impedance, and material definition: define and negotiate layer stackups,&nbsp;dielectric materials, impedance targets, and loss budgets with fabricators, and select&nbsp;constructions that meet electrical, thermal, and cost objectives.</div>
<div style="color: black;">&bull; Constraint management and timing closure: build and maintain constraint sets in&nbsp;Cadence Allegro Constraint Manager, including differential pair phase tuning, delay and&nbsp;skew matching, T-topologies, Z-axis delay compensation, crosstalk control, and return-path continuity.</div>
<div style="color: black;">&bull; Power distribution layout: lay out high-current power delivery for accelerator-class&nbsp;devices, covering plane and shape partitioning, copper weight and thermal via strategy,decoupling placement, and PDN loop inductance minimization in coordination with&nbsp;power integrity engineers.</div>
<div style="color: black;">&bull; Simulation-driven iteration: work with signal and power integrity engineers to extract&nbsp;critical channels and planes, interpret results, and iterate placement, stackup, and&nbsp;routing until the design meets its margins.</div>
<div style="color: black;">&bull; Manufacturability and release: drive DFM, DFA, and DFT reviews with fab and&nbsp;assembly vendors, maintain footprint and padstack libraries and ECAD data integrity,&nbsp;and produce complete, unambiguous release packages in Gerber, ODB++, or IPC-2581.<br><br></div>
<div style="color: black;"><strong>Requirements</strong></div>
<div style="color: black;">&bull; Diploma, Bachelor&rsquo;s, or equivalent qualification in Electrical or Electronics Engineering,&nbsp;or equivalent professional PCB design experience.</div>
<div style="color: black;">&bull; 8+ years of high-speed, high-density PCB layout experience, with a strong focus on&nbsp;server, networking, or AI accelerator hardware.</div>
<div style="color: black;">&bull; Expert-level proficiency in Cadence Allegro including Constraint Manager; Altium&nbsp;Designer or Siemens Xpedition experience is a plus.</div>
<div style="color: black;">&bull; Proven track record laying out high layer count boards, ideally 16 layers and above,&nbsp;using HDI, sequential lamination, via-in-pad and VIPPO, blind and buried vias, and&nbsp;controlled-depth backdrilling.</div>
<div style="color: black;">&bull; Demonstrated routing of at least two of the following interface families to closure: PCIe&nbsp;Gen5/6, LPDDR5, GDDR6/7, HBM-adjacent interfaces, 400G/800G Ethernet.</div>
<div style="color: black;">&bull; Hands-on experience with escape routing from large, fine-pitch BGA packages and&nbsp;dense land grid footprints.</div>
<div style="color: black;">&bull; Solid grasp of stackup and material selection, impedance control, insertion loss&nbsp;budgeting, and how fabrication tolerances affect real channel performance.</div>
<div style="color: black;">&bull; Competence in high-current power plane layout, thermal via and copper weight&nbsp;decisions, and decoupling placement for PDN performance.</div>
<div style="color: black;">&bull; Working knowledge of IPC standards including IPC-2221, IPC-2222, IPC-6012, and&nbsp;IPC-7351, plus practical DFM, DFA, and DFT rule sets from real production builds.</div>
<div style="color: black;">&bull; Experience collaborating with signal and power integrity engineers, mechanical&nbsp;designers, and fabricators, including running layout and DFM reviews directly with&nbsp;vendors.</div>
<div style="color: black;">&bull; Strong communication and documentation skills, with the discipline to keep libraries,&nbsp;constraints, revisions, and release data clean and traceable.<br><br></div>
<div style="color: black;"><strong>Preferred Qualifications (Nice-to-Haves)</strong></div>
<div style="color: black;">&bull; IPC CID or CID+ certification.</div>
<div style="color: black;">&bull; Automation and scripting experience with Allegro SKILL or equivalent to accelerate&nbsp;repetitive layout and checking tasks.</div>
<div style="color: black;">&bull; Direct use of extraction and simulation tools such as Cadence Sigrity and PowerSI,&nbsp;Ansys SIwave or HFSS, or Clarity, and the ability to close loops without waiting on a&nbsp;specialist.<br>&bull; Experience with AI accelerator and data center form factors such as OAM, UBB, SXM,&nbsp;PCIe CEM, or OCP and DC-MHS compliant boards, including liquid-cooled and cold-plate constrained layouts.</div>
<div style="color: black;">&bull; Rigid-flex, press-fit connector, cable, and backplane or midplane layout experience.</div>
<div style="color: black;">&bull; Mechanical co-design fluency with STEP exchange and tools such as SolidWorks, Creo,&nbsp;or NX for tightly packaged, high-power assemblies.<br><br></div>
<div style="color: black;"><strong>Why Join Us</strong></div>
<div style="color: black;">&bull; Route the boards that carry our own AI silicon, where your stackup and escape strategy&nbsp;decisions directly set the performance ceiling of the product.</div>
<div style="color: black;">&bull; Sit inside the engineering team rather than at the end of a handoff chain, working daily&nbsp;with board design, signal integrity, package, and mechanical engineers.</div>
<div style="color: black;">&bull; Take on genuinely hard layout problems, from dense ASIC package escapes to first-of-&nbsp;a-kind bring-up fixtures, with the tooling and vendor access to do them properly.</div>
<div style="color: black;">&bull; Competitive compensation, growth opportunities, and the chance to help define the&nbsp;platform that powers advanced AI workloads.<br><br></div>
<div style="color: black;"><strong>Ready to Accelerate the Future of AI?</strong></div>
<div style="color: black;">If you&rsquo;re passionate about closing impossible-looking channels and power planes on dense,</div>
<div style="color: black;">high layer count boards &mdash; we&rsquo;d love to hear from you.</div>
<div style="color: black;">Apply now and help us deliver production-ready platforms that make AI faster, safer, and more</div>
<div style="color: black;">efficient.</div>
</div>

<div style="color: black;">
<div style="color: black;"><span class="large bold" style="font-size: 1.125rem; color: black; font-weight: bold;">About Us</span></div>
<div style="color: black;">We are a tech company specializing in the design and development of cutting-edge, customized server hardware solutions optimized for artificial intelligence and machine learning applications. Our mission is to empower businesses and researchers to accelerate their AI initiatives by providing them with high-performance, scalable, and energy-efficient hardware infrastructure.</div>
<div style="color: black;">As a rapidly growing company at the forefront of AI hardware innovation, we are constantly seeking talented and motivated individuals to join our team. We offer a dynamic and challenging work environment, with opportunities to make a significant impact on the future of AI technology.</div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;"><span class="large bold" style="font-size: 1.125rem; color: black; font-weight: bold;">You'll Collaborate With</span></div>
<div style="color: black;">Firmware, silicon, runtime, datacenter software and architects teams to deliver a robust kernel foundation that integrates seamlessly with modern datacenter environments and AI workloads.</div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;"><span class="large bold" style="font-size: 1.125rem; color: black; font-weight: bold;">What You'll Own</span></div>
<ul>
<li style="color: black;">
<div style="color: black;"><strong>PCIe Foundation</strong>: Design and implement robust PCIe kernel drivers for AI accelerator enumeration, configuration, and management that form the critical host-device communication backbone.</div>
</li>
<li style="color: black;">
<div style="color: black;"><strong>High-Speed Data Movement</strong>: Develop DMA engines and memory management systems that deliver zero-copy, high-throughput data movement between host and accelerator for massive AI workloads.</div>
</li>
<li style="color: black;">
<div style="color: black;"><strong>Firmware Bridge</strong>: Build interrupt handling (MSI/MSI-X) and mailbox communication protocols that create seamless coordination between kernel space and our firmware stack.</div>
</li>
<li style="color: black;">
<div style="color: black;"><strong>System Observability</strong>: Create comprehensive sysfs/debugfs interfaces for device configuration, telemetry, and diagnostics that give operators deep visibility into accelerator operations.</div>
</li>
<li style="color: black;">
<div style="color: black;"><strong>Multi-Die Orchestration</strong>: Support multi-die topologies through device discovery, link management, and topology coordination that scales from single-card to cluster deployments.</div>
</li>
<li style="color: black;">
<div style="color: black;"><strong>Power &amp; Thermal Intelligence</strong>: Develop power management and thermal control integration with Linux PM frameworks that optimize performance while maintaining reliability.</div>
</li>
<li style="color: black;">
<div style="color: black;"><strong>Reliability Engineering</strong>: Contribute to device health monitoring, error handling (RAS), and recovery mechanisms that deliver the 99.99% uptime datacenter customers require.</div>
</li>
<li style="color: black;">
<div style="color: black;"><strong>Performance Optimization</strong>: Optimize kernel-space performance for AI workloads, focusing on latency, throughput, and scalability that directly impacts model training and inference speed.</div>
</li>
<li style="color: black;">
<div style="color: black;"><strong>Time Synchronization</strong>: Support PTP/PHC time synchronization for distributed training and inference that ensures coordination across multi-node AI clusters.</div>
</li>
<li style="color: black;">
<div style="color: black;"><strong>Runtime Partnership</strong>: Collaborate with userspace runtime teams on kernel-userspace interfaces and APIs that enable efficient scheduling and resource sharing.</div>
</li>
<li style="color: black;">
<div style="color: black;"><strong>Future-Ready Architecture</strong>: Lay the groundwork for device virtualization and multi-tenant isolation, ensuring our platform can evolve with customer needs.</div>
</li>
</ul>
<div style="color: black;"><span class="large bold" style="font-size: 1.125rem; color: black; font-weight: bold;">Minimum Qualifications</span></div>
<ul>
<li style="color: black;">
<div style="color: black;">5+ years developing Linux kernel drivers and subsystems in C for complex SoCs or accelerators</div>
</li>
<li style="color: black;">
<div style="color: black;">Proven experience with PCIe device driver development (enumeration, BARs, DMA, interrupts)</div>
</li>
<li style="color: black;">
<div style="color: black;">Strong knowledge of Linux memory management, DMA mapping, and IOMMU integration</div>
</li>
<li style="color: black;">
<div style="color: black;">Hands-on experience with kernel synchronization primitives, workqueues, and interrupt handling</div>
</li>
<li style="color: black;">
<div style="color: black;">Solid understanding of Linux device model, sysfs/debugfs, and driver lifecycle management</div>
</li>
<li style="color: black;">
<div style="color: black;">Familiarity with kernel debugging tools: ftrace, perf, crash, kprobes, and hardware debuggers</div>
</li>
<li style="color: black;">
<div style="color: black;">Ability to read hardware specifications and work with RTL/hardware teams on register interfaces</div>
</li>
<li style="color: black;">
<div style="color: black;">Excellent documentation habits; comfortable with kernel development processes and upstream contribution</div>
</li>
</ul>
<div style="color: black;"><span class="large bold" style="font-size: 1.125rem; color: black; font-weight: bold;">Preferred Qualifications</span></div>
<ul>
<li style="color: black;">
<div style="color: black;">Experience with AI/ML accelerator drivers or GPU compute drivers (NVIDIA, AMD, Intel)</div>
</li>
<li style="color: black;">
<div style="color: black;">Implemented RDMA/RoCE drivers or high-speed networking kernel subsystems</div>
</li>
<li style="color: black;">
<div style="color: black;">Background in PTP/PHC time synchronization or distributed system timing</div>
</li>
<li style="color: black;">
<div style="color: black;">Multi-die/chiplet device driver experience and topology management</div>
</li>
<li style="color: black;">
<div style="color: black;">Linux kernel upstream contributions and familiarity with kernel community processes</div>
</li>
<li style="color: black;">
<div style="color: black;">Experience with kernel security features, SELinux integration, and device isolation</div>
</li>
<li style="color: black;">
<div style="color: black;">Knowledge of container/runtime integration with kernel drivers (Docker, Kubernetes)</div>
</li>
<li style="color: black;">
<div style="color: black;">Performance optimization experience for high-throughput, low-latency kernel subsystems</div>
</li>
<li style="color: black;">
<div style="color: black;">Familiarity with RAS concepts, ECC handling, and system reliability in kernel space</div>
</li>
</ul>
<div style="color: black;"><span class="large bold" style="font-size: 1.125rem; color: black; font-weight: bold;">What Success Looks Like (First 6&ndash;9 Months)</span></div>
<ul>
<li style="color: black;">
<div style="color: black;">PCIe driver is stable and reliable across multiple system configurations and stress tests</div>
</li>
<li style="color: black;">
<div style="color: black;">DMA and memory management achieve target throughput with low CPU overhead</div>
</li>
<li style="color: black;">
<div style="color: black;">Multi-die topology management and inter-card communication is functional and performant</div>
</li>
<li style="color: black;">
<div style="color: black;">Integration with firmware mailbox protocols and telemetry collection is operational</div>
</li>
<li style="color: black;">
<div style="color: black;">Performance benchmarks meet targets for key AI workloads (inference and training)</div>
</li>
<li style="color: black;">
<div style="color: black;">Documentation and test coverage enable team-wide development and deployment</div>
</li>
</ul>
<div style="color: black;"><strong>Ready to accelerate the future of AI from the firmware up?</strong></div>
<div style="color: black;">Submit your application with links to relevant firmware projects, papers, or upstream contributions demonstrating secure boot, update/recovery, PCIe bring-up, or runtime management. Show us how you think systematically about firmware architecture and what you've built that scales.</div>
<div style="color: black;"><em style="color: black;">Join us in our mission to democratize AI compute &mdash; where your firmware expertise becomes the bedrock of tomorrow's AI breakthroughs.</em></div>
</div>

<div style="color: black;">
<div style="color: black;"><strong>Description</strong>&nbsp;</div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;">We are a technology company focused on designing and developing advanced, customized server hardware solutions optimized for artificial intelligence workloads. Our mission is to accelerate AI innovation by delivering high-performance, scalable, and energy-efficient infrastructure for datacenter-scale inference.&nbsp;</div>
<div style="color: black;">Our chips in development are purpose-built for large-scale AI inference and will be deployed in rack-level systems where multiple devices collaborate to deliver optimal latency, throughput, and efficiency. We are building the next generation of AI infrastructure and are looking for engineers who deeply understand how modern large language models behave at scale.&nbsp;</div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;">This role is focused on LLM systems, architecture, and performance. You will work at the intersection of model internals and hardware, ensuring that state-of-the-art models run efficiently on our platform.&nbsp;</div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;">
<div style="color: black;"><strong>Responsibilities</strong>&nbsp;</div>
<ul>
<li style="color: black;">
<div style="color: black;">Analyze, profile and optimize large language model (LLM) inference performance across distributed, multi-chip systems&nbsp;</div>
</li>
</ul>
<ul>
<li style="color: black;">
<div style="color: black;">Bring a deep understanding of transformer architectures, including dense and Mixture-of-Experts (MoE) models&nbsp;</div>
</li>
</ul>
<ul>
<li style="color: black;">
<div style="color: black;">Evaluate and benchmark different LLMs (e.g., LLaMA, Mistral, Qwen, DeepSeek) on custom hardware&nbsp;</div>
</li>
</ul>
<ul>
<li style="color: black;">
<div style="color: black;">Design and implement optimizations for attention mechanisms (e.g., Flash Attention, grouped-query attention, sliding window attention)&nbsp;</div>
</li>
</ul>
<ul>
<li style="color: black;">
<div style="color: black;">Work on model-level optimizations such as quantization (INT8/FP8), KV-cache management, batching, and parallelism strategies&nbsp;</div>
</li>
</ul>
<ul>
<li style="color: black;">
<div style="color: black;">Collaborate with hardware and compiler teams to co-design efficient inference pipelines&nbsp;</div>
</li>
</ul>
<ul>
<li style="color: black;">
<div style="color: black;">Build and maintain benchmarking frameworks to evaluate latency, throughput, and scaling behavior&nbsp;</div>
</li>
</ul>
<ul>
<li style="color: black;">
<div style="color: black;">Analyze trade-offs between model architecture choices and system-level performance&nbsp;</div>
</li>
</ul>
<ul>
<li style="color: black;">
<div style="color: black;">Contribute to model deployment strategies for large-scale datacenter environments&nbsp;</div>
</li>
</ul>
<ul>
<li style="color: black;">
<div style="color: black;">Stay up to date with the latest research in LLM architectures and inference optimization&nbsp;</div>
</li>
</ul>
<div style="color: black;">&nbsp;</div>
<div style="color: black;"><strong>Requirements</strong>&nbsp;</div>
<ul>
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<div style="color: black;">Strong understanding of transformer architectures and LLM internals&nbsp;</div>
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<div style="color: black;">Hands-on experience working with multiple modern LLMs (e.g., LLaMA, Mistral, Qwen, DeepSeek, etc.)&nbsp;</div>
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<div style="color: black;">Deep knowledge of different LLM architectures such as dense models and Mixture-of-Experts (MoE) architectures&nbsp;</div>
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<div style="color: black;">Familiarity with attention mechanisms and their optimizations&nbsp;</div>
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<div style="color: black;">Experience with LLM inference optimization techniques (quantization, pruning, KV caching, batching, etc.)&nbsp;</div>
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<div style="color: black;">Strong Python skills and experience with ML frameworks (PyTorch, JAX, or similar)&nbsp;</div>
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<div style="color: black;">Experience with distributed systems and large-scale inference workloads&nbsp;</div>
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<div style="color: black;">Ability to profile and debug performance bottlenecks across hardware and software stacks&nbsp;</div>
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<div style="color: black;">Strong systems thinking and ability to work across model, runtime, and hardware layers&nbsp;</div>
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<div style="color: black;">&nbsp;</div>
<div style="color: black;"><strong>Preferred Qualifications</strong>&nbsp;</div>
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<div style="color: black;">8+ years of relevant experience in deep learning, AI systems, or performance engineering&nbsp;</div>
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<div style="color: black;">Experience working close to hardware (GPU, TPU, or custom accelerators)&nbsp;</div>
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<div style="color: black;">Experience with parallelism strategies (tensor parallelism, pipeline parallelism, expert parallelism)&nbsp;</div>
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<div style="color: black;">Familiarity with datacenter-scale deployment, orchestration and inference servers (e.g., vLLM)&nbsp;</div>
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<div style="color: black;">Background in performance engineering or systems optimization&nbsp;</div>
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<div style="color: black;">&nbsp;</div>
<div style="color: black;"><strong>What We&rsquo;re Not Looking For</strong>&nbsp;</div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;">This role is <strong>not focused on prompt engineering, or application-layer GenAI development</strong>. Instead, it is centered on <strong>deep LLM internals, architecture, and inference performance at scale</strong>.&nbsp;</div>
<div style="color: black;">&nbsp;</div>
<div style="color: black;"><strong>Why Join Us?</strong>&nbsp;</div>
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<div style="color: black;">Work on cutting-edge AI hardware designed specifically for LLM inference&nbsp;</div>
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<div style="color: black;">Solve challenging problems at the intersection of AI models and systems&nbsp;</div>
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<div style="color: black;">Collaborate with a team pushing the boundaries of datacenter-scale AI performance&nbsp;</div>
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<div style="color: black;">Make a direct impact on the future of AI infrastructure&nbsp;</div>
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