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evollabs tech.

<p><span style="background-color:rgb(255,255,255);color:rgb(0,0,0);font-family:Inter, &quot;Inter Fallback&quot;;"><span style="-webkit-text-stroke-width:0px;display:inline !important;float:none;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">As an SDET, you will design and implement automated tests, CI/CD pipelines, and orchestration tools that ensure the reliability of our </span></span><strong style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:rgb(0, 0, 0);font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:bolder;letter-spacing:normal;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">next-generation Network Operating System (NOS)</strong><span style="background-color:rgb(255,255,255);color:rgb(0,0,0);font-family:Inter, &quot;Inter Fallback&quot;;"><span style="-webkit-text-stroke-width:0px;display:inline !important;float:none;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">. You’ll act as the engineering link between developers and testers, writing robust test frameworks and simulation environments to validate functionality at scale.</span></span></p>

About the Role

<ul><li>Design and implement automated test frameworks for NOS features and protocols.</li><li>Extend CI/CD pipelines for continuous integration and automated regression testing.</li><li>Write and maintain Python and Bash code for simulation, orchestration, and validation.</li><li>Build automated test suites using <strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">pytest, nose, or similar frameworks</strong>.</li><li>Collaborate with developers to build test hooks into new features.</li><li>Debug test failures and improve test reliability and performance.</li></ul>

What You’ll Do

<ul><li>3+ years of experience in networking or systems testing.</li><li>Strong Python coding skills (classes, decorators, threading).</li><li>Experience with <strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">pytest or nose</strong> (test case structuring, fixtures, reporting).</li><li>Familiarity with Linux OS internals, containers, and virtualization.</li><li>Hands-on experience with Ethernet/IP networking fundamentals (BGP, OSPF, ACLs).</li><li>Proficiency with Git and modern CI/CD pipelines (Jenkins preferred).</li></ul>

What We’re Looking For

SDET (Networking, Python)

<p><span style="background-color:rgb(255,255,255);color:rgb(0,0,0);font-family:Inter, &quot;Inter Fallback&quot;;"><span style="-webkit-text-stroke-width:0px;display:inline !important;float:none;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">As a Senior SDET, you’ll </span></span><strong style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:rgb(0, 0, 0);font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:bolder;letter-spacing:normal;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">architect and lead test automation</strong><span style="background-color:rgb(255,255,255);color:rgb(0,0,0);font-family:Inter, &quot;Inter Fallback&quot;;"><span style="-webkit-text-stroke-width:0px;display:inline !important;float:none;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;"> for complex networking features, scaling frameworks to validate control plane, data plane, and hardware-software interactions. You’ll drive best practices in test development and mentor junior SDETs.</span></span></p>

<ul><li>Architect large-scale automated testing systems for data center and telco networking.</li><li>Design simulation environments reproducing customer topologies (BGP EVPN fabrics, MPLS backbones).</li><li>Lead CI/CD strategy for continuous, automated validation of NOS builds.</li><li>Build and extend advanced test suites using <strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">pytest, nose, or equivalent frameworks</strong>.</li><li>Mentor SDETs and QA engineers in coding and automation practices.</li><li>Partner with development leads to ensure test coverage aligns with feature roadmaps.</li></ul>

<ul><li>6+ years of experience in test automation, preferably in networking or systems.</li><li>Strong expertise in Python and Bash; capable of building 10k+ LOC frameworks.</li><li>Proven experience in <strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">test automation frameworks (pytest/nose)</strong> and scaling them.</li><li>Deep knowledge of data center networking protocols (BGP, EVPN, MPLS).</li><li>Experience with Jenkins, Ansible, and Git-based workflows.</li></ul>

Sr SDET (Networking, Python)

<p><span style="background-color:rgb(255,255,255);color:rgb(0,0,0);font-family:Inter, &quot;Inter Fallback&quot;;font-size:18px;"><span style="-webkit-text-stroke-width:0px;display:inline !important;float:none;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">As QA Team Lead, you will build and guide a team of QA Engineers and SDETs responsible for the </span></span><span style="font-size:18px;"><strong style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:rgb(0, 0, 0);font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:bolder;letter-spacing:normal;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">quality of our NOS</strong></span><span style="background-color:rgb(255,255,255);color:rgb(0,0,0);font-family:Inter, &quot;Inter Fallback&quot;;font-size:18px;"><span style="-webkit-text-stroke-width:0px;display:inline !important;float:none;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">. You’ll balance </span></span><span style="font-size:18px;"><strong style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:rgb(0, 0, 0);font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:bolder;letter-spacing:normal;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">technical leadership</strong></span><span style="background-color:rgb(255,255,255);color:rgb(0,0,0);font-family:Inter, &quot;Inter Fallback&quot;;font-size:18px;"><span style="-webkit-text-stroke-width:0px;display:inline !important;float:none;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;"> (test strategy, automation design) with </span></span><span style="font-size:18px;"><strong style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:rgb(0, 0, 0);font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:bolder;letter-spacing:normal;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">people leadership</strong></span><span style="background-color:rgb(255,255,255);color:rgb(0,0,0);font-family:Inter, &quot;Inter Fallback&quot;;font-size:18px;"><span style="-webkit-text-stroke-width:0px;display:inline !important;float:none;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;"> (mentorship, team development, delivery accountability).</span></span></p>

<ul><li>Lead and mentor a QA team (5–10 engineers) across manual and automated testing.</li><li>Define QA strategy for functional, regression, and performance validation.</li><li>Oversee CI/CD pipeline integration of QA workflows.</li><li>Coordinate test planning with development leads across HAL, Control Plane, and Management Plane.</li><li>Ensure timely and high-quality delivery of test cycles.</li><li>Act as the voice of QA in release and architecture reviews.</li></ul>

<ul><li>Proven experience leading QA teams in networking or systems software.</li><li>Strong technical background in test automation and network engineering.</li><li>Familiarity with major routing protocols and data center networking.</li><li>Experience managing CI/CD-driven QA environments.</li><li>Excellent communication and leadership skills.</li></ul>

<p><span style="background-color:rgb(255,255,255);color:rgb(0,0,0);font-family:Inter, &quot;Inter Fallback&quot;;"><span style="-webkit-text-stroke-width:0px;display:inline !important;float:none;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">You will </span></span><strong style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:rgb(0, 0, 0);font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:bolder;letter-spacing:normal;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">own the quality culture</strong><span style="background-color:rgb(255,255,255);color:rgb(0,0,0);font-family:Inter, &quot;Inter Fallback&quot;;"><span style="-webkit-text-stroke-width:0px;display:inline !important;float:none;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;"> of a greenfield NOS project — building not only a product but also a QA discipline that sets benchmarks for MENAT and beyond.</span></span></p>

Career Opportunity

Team Lead - QA

<p><span style="background-color:rgb(255,255,255);color:rgb(0,0,0);font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;"><span style="-webkit-text-stroke-width:0px;display:inline !important;float:none;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">Own the end-to-end </span></span><strong style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:rgb(0, 0, 0);font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:bolder;letter-spacing:normal;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">verification</strong><span style="background-color:rgb(255,255,255);color:rgb(0,0,0);font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;"><span style="-webkit-text-stroke-width:0px;display:inline !important;float:none;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;"> of critical ASIC subsystems—from compute pipelines and high-speed I/O to interconnects and multi-die coherency. You’ll architect UVM environments and golden reference models, turn specs into assertions and checkers, drive coverage to closure, and tie in emulation/FPGA and SW-in-the-loop to catch bugs before tape-out. This is where one missed corner case can cost millions—finding it early keeps our AI silicon on schedule and on target.</span></span></p>

Your Mission

<ul><li><strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">Own block-to-subsystem verification</strong>: author verification plans from specs, define stimulus/coverage strategy, and deliver sign-off with data (functional/code/assertion coverage).</li><li><strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">Build scalable UVM environments</strong>: agents, monitors, scoreboards, sequences, reference models (C++/Python/DPI), protocol checkers, and reusable components.</li><li><strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">Exercise real workloads</strong>: co-sim with firmware/drivers, run emulation/FPGA prototypes, and correlate performance/behavior with architectural models.</li><li><strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">Apply assertions &amp; formal</strong>: write SVA, run formal where appropriate (protocol/liveness/safety), and integrate results into overall coverage.</li><li><strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">Close quality gates</strong>: lint/CDC/RDC verification collaboration, gate-level/reset/power-up scenarios, low-power (UPF) intent checks.</li><li><strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">Harden regressions</strong>: own CI pipelines, randomized/constrained tests, triage failures, root-cause with RTL/design, and track fixes to closure.</li><li><strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">Interface &amp; document</strong>: keep specs, test plans, coverage dashboards, and bug reports clear for Architects, RTL, Firmware/Drivers, and DFT/PD teams.</li></ul>

Responsibilities

<p><span style="background-color:rgb(255,255,255);color:rgb(0,0,0);font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;"><span style="-webkit-text-stroke-width:0px;display:inline !important;float:none;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">Silicon architects (clarifying intent and performance targets), RTL designers (debug and ECOs), firmware and Linux driver teams (HW/SW co-verification), performance architects (workload traces and counters), and EDA/CAD (flows, regressions, metrics) to ensure first-pass silicon success.</span></span></p>

You'll Collaborate With

<ul><li>7+ years in ASIC/SoC verification with <strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">SystemVerilog/UVM</strong> (ownership from test plan to sign-off).</li><li>Strong command of <strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">constrained-random stimulus</strong>, <strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">scoreboarding</strong>, <strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">coverage-driven</strong> verification, and <strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">SVA</strong>.</li><li>Hands-on with major simulators (e.g., VCS/Questa/Xcelium) and regression/CI tooling.</li><li>Familiarity with standard protocols (AMBA, AXI, APB, AHB) and industrial VIPs</li><li>Experience verifying complex IP/subsystems (at least one of: multi-core compute, NoC/coherency, high-speed I/O like PCIe, Ethernet 100/400G, HBM/DDR, UCIe).</li><li>Proficient in scripting for automation (Python/TCL/Make) and building reusable verification components.</li><li>Solid understanding of SoC fundamentals: resets, clocking, CDC/RDC, back-pressure/flow control, performance counters.</li></ul>

Minimum Qualifications

<ul><li>Emulation/FPGA prototyping (Palladium/Zebu/Veloce; Xilinx/Intel) and SW-in-the-loop setups.</li><li>Formal verification experience (JasperGold/VC Formal) and assertion methodology leadership.</li><li>DFT/DFD awareness and post-silicon bring-up experience.</li><li>Exposure to AI accelerator domains (systolic/dataflow, memory hierarchies, tiling) and traffic modeling.</li><li>Experience building coverage dashboards and integrating verification metrics into CI/CD.</li><li>Experience with C/C++/DPI for RTL Co-Simulation.</li></ul>

Preferred Qualifications (Nice-to-Have)

ASIC Verification Engineer (Athens Office)

<p><span style="background-color:rgb(255,255,255);color:rgb(0,0,0);font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;"><span style="-webkit-text-stroke-width:0px;display:inline !important;float:none;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">Own the end-to-end design of critical ASIC subsystems—from PLLs and compute clusters to interconnects and multi-die orchestration. The RTL you build becomes production silicon and moves real AI workloads faster. This is where microseconds, watts, and millimeters directly impact AI economics at scale.</span></span></p>

<ul><li><strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">Own complex ASIC subsystems end-to-end</strong>: specification, architectural exploration, IP evaluation/selection, integration, verification planning, and post-silicon validation</li><li><strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">Make architecture/micro-architecture trade-offs</strong> across features, performance, power, and area; define clean interfaces and write production-quality RTL (Verilog/SystemVerilog).</li><li><strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">Implement and verify</strong> at block and subsystem levels (UVM/formal where appropriate); set coverage goals and drive sign-off.</li><li><strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">Develop constraints and close timing</strong>: author SDC, run STA (setup/hold, OCV/derates), perform CDC/RDC analysis, and collaborate with PD on floorplanning and CTS.</li><li><strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">Simulate and emulate</strong> (FPGA/emulator), debug waveforms/logs, and correlate pre-/post-silicon behavior.</li><li><strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">Define and implement DFT/DFD</strong> (scan, MBIST/LBIST, boundary scan/JTAG); support ATPG and test bring-up.</li><li><strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">Maintain code quality</strong> with lint, CDC/RDC, LEC, and synthesis-friendly design practices; drive ECOs as needed.</li><li><strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">Build timing/debug automation</strong>: create Tcl/PrimeTime scripts for skew analysis, clock dividers/special clocks, and core-to-IO interfaces (PCIe, 400GE, UCIe).</li><li><strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">Document clearly</strong>: specifications, micro-architecture, interfaces, and user guides for downstream teams.</li></ul>

<p><span style="background-color:rgb(255,255,255);color:rgb(0,0,0);font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;"><span style="-webkit-text-stroke-width:0px;display:inline !important;float:none;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">Our silicon architects designing the next breakthrough in AI compute, verification engineers, Linux driver and firmware engineers building the software stack, security teams protecting customer assets, compiler and ML framework teams optimizing workload mapping, and system validation engineers ensuring enterprise reliability — together, we're building the infrastructure that makes AI accessible and powerful</span></span></p>

<ul><li>7+ years of experience in RTL design and ASIC development (verilog/systemverilog is preferred)</li><li>Hands-on experience in all aspects of the chip development process with proficiency in front end tools and methodologies</li><li>Experience with configuration and integration of a complex IPs <strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">is a must</strong> (at least one of the following: multi-core CPUs, NOCs, custom accelerators aka GPU/NPU or high-speed interfaces like PCIe, 100/400G Ethernet, UCIe)</li><li>Experience writing specifications and converting them into design</li><li>Experience with multiple clock domains and asynchronous interfaces</li><li>Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB)</li></ul>

<ul><li>Experience with power and clock management designs</li><li>Formal Equivalency Checking RTL to Netlist</li><li>Experience with DFT</li><li>Understanding of AI accelerator architectures (systolic arrays, dataflow, tiling) and memory bandwidth optimization</li><li>Experience with HBM/GDDR integration or other high-bandwidth memory subsystems</li></ul>

Preferred Qulifications (Nice-to-Have)

<ul><li>First silicon boots and runs real AI workloads (not just benchmarks)</li><li>PPA targets met: performance/watt competitive with industry leaders</li><li>Compiler team can generate efficient code without hardware workarounds</li><li>Mean time to debug customer issues: &lt;24 hours</li></ul>

What Success Really Means

<p>Submit your application with links to relevant projects, papers, or recommendations. Show us how you think systematically about RTL design and what you've built that scales.</p><p><em style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;margin:0px;padding:0px;"><i>Join us in our mission to democratize AI compute — where your RTL expertise becomes the bedrock of tomorrow's AI breakthroughs.</i></em></p>

Ready to accelerate the future of AI?

RTL Developer (Athens Office)

<p><span style="color:black;font-size:1.125rem;"><span class="large" style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;margin:0px;padding:0px;">We are building a next-generation AI ASIC and need to validate it comprehensively before tape-out. As a Staff System-Level Verification Engineer, you will develop the software infrastructure, models, and testbenches that prove our hardware design meets specifications and integrates seamlessly with the full software stack—from firmware to host drivers.</span></span></p><p><span style="color:black;font-size:1.125rem;"><span class="large" style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;margin:0px;padding:0px;">You will operate at the critical intersection of RTL design and system software, creating pre-silicon verification environments that catch bugs early, validate programming interfaces, and enable firmware and driver development months before silicon arrives. Working within a collaborative cross-functional team of UVM verification engineers, RTL designers, architects, and software developers, you will anchor the system-software verification layer and directly influence tape-out confidence and time-to-market.</span></span></p>

Job description

<ul><li>Develop and maintain System Verification Plan</li><li>Create and validate programming sequences for hardware initialization, configuration, and runtime operations</li><li>Own the C/C++-based system-level test infrastructure and SystemVerilog DPI-C interfaces</li><li>Collaborate with the UVM team on sequence integration, coverage alignment, and regression interoperability</li><li>Analyze simulation waveforms to debug hardware-software interactions, protocol violations, and timing issues</li><li>Implement verification testbenches covering functional scenarios, corner cases, error injection, and recovery paths</li><li>Collaborate with RTL designers to reproduce bugs, validate fixes, and close verification gaps</li><li>Create stimulus generators and reference models for data-path validation and result checking</li><li>Build regression frameworks with coverage tracking and automated reporting</li><li>Develop C/C++ test sequences that execute representative AI workloads (provided by architecture/ML teams), including graph dispatch, tensor movement, and synchronization.</li><li>Validate the command and control interface (e.g., mailboxes, doorbells) from the host driver to the accelerator's firmware and hardware schedulers.</li></ul>

<ul><li>5+ years in pre-silicon verification, hardware–software co-verification, or system-level modeling for SoCs or accelerators</li><li>Proficiency in reading RTL (Verilog/SystemVerilog) and co-designing SystemVerilog DPI-C interfaces to connect C/C++ testbenches with the UVM simulation environment.</li><li>Proven experience developing register models and validating programming sequences against RTL across multiple subsystems</li><li>Hands-on expertise with AMBA protocols (AXI/APB): outstanding transactions, ordering rules, back-pressure, error responses</li><li>Proficiency analyzing waveforms to root-cause protocol, ordering, and timing issues</li><li>Solid C/C++ for testbench infrastructure, reference models, and verification components; Python/Perl/Tcl for automation</li><li>Experience with industry simulators (VCS/Questa/Xcelium) and waveform viewers (Verdi/DVE/Simvision)</li><li>Familiarity with at least one of: PCIe Gen5/Gen6 (PF/VF, SR-IOV), Ethernet 400/800G with RoCEv2, HBM memory controllers, NoC topologies/QoS, RISC-V firmware bring-up</li><li>Excellent debug methodology: clear hypotheses, minimal reproductions, crisp bug reports and fixes</li></ul>

<ul><li>Pre-silicon verification experience on AI/ML accelerators, GPUs, or high-performance compute engines</li><li>Experience driving UVM sequences and monitors from a C/C++ test harness.</li><li>PCIe, SR-IOV/virtualization, Ethernet/RDMA, HBM/DDR controllers, or NoC verification; experience with protocol compliance suites and VIPs</li><li>Experience with FPGA prototyping for pre-silicon validation</li><li>Firmware or Linux driver development background enabling deep understanding of software requirements</li><li><p>Exposure to security verification concepts such as fault injection or secure boot validation</p><p>&nbsp;</p></li></ul>

Preferred Qualifications

<ul><li>&gt;95% functional coverage on user-defined scenarios and error recovery paths, as defined in the System Verification Plan</li><li>IO and NoC infrastructure validated against key use cases (single-card inference/training, multi-card with RDMA)</li><li>System-level regression runs full AI workload scenarios (e.g., model graph initialization, execution, and result readback) using the C/C++ test infrastructure.</li><li>Nightly regressions with coverage tracking and trend dashboards; clear metrics track closure by subsystem and use case</li><li>Documentation (register specs, programming guides, timing diagrams, bring-up checklists) unblocks parallel software development</li></ul>

What Success Looks Like

<ul><li>Simulators: VCS, Questa, Xcelium, Verilator; waveform viewers: Verdi, DVE, Simvision</li><li>Protocol VIPs/compliance: PCIe Gen5/Gen6 VIP, Ethernet/RoCE VIP, HBM controller models, NoC traffic generators; UCIe/BoW VIP for chiplet flows</li><li>Build &amp; automation: Python (cocotb, pytest), Tcl, Makefiles, CMake, Bazel</li><li>Coverage: IMC, Visualizer, custom coverage dashboards</li><li>Version control &amp; CI: Git, Jenkins, GitLab CI, regression management systems</li></ul>

Nice-to-Have Tooling

Staff SW Pre-Silicon System Verification Engineer

<div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;"><strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">Team:</strong> SoC Physical Design Team</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;"><strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">Type:</strong> Full-time – On-site</div>

<p>We&nbsp;design and develop&nbsp;customized server hardware solutions optimized for artificial intelligence and machine learning workloads. Our focus is on high-performance, scalable, and energy-efficient infrastructure for next-generation AI compute.</p><p>&nbsp;</p>

About Us

<p>Evollabs Tech is hiring a <strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">Senior DFT Engineer</strong> to own design-for-test architecture, implementation, verification, and silicon bring-up for advanced AI SoC / ASIC accelerator designs.</p><p>This role will work across RTL, verification, physical design, product engineering, ATE, and external partners to deliver testable, diagnosable, production-ready silicon.</p>

Role Overview

<ul><li>Define and implement DFT architectures for complex AI SoC/ASIC blocks and subsystems.</li><li>Own scan insertion, scan compression, ATPG, fault coverage closure, and DFT signoff.</li><li>Implement and support MBIST, LBIST, JTAG, boundary scan, test access, and memory repair features.</li><li>Develop DFT specifications, test plans, coverage targets, constraints, and signoff criteria.</li><li>Work with RTL and verification teams to ensure DFT requirements are built into the design early.</li><li>Collaborate with physical design teams on scan reordering, test-mode timing, congestion, ECOs, and implementation closure.</li><li>Debug DFT issues across RTL, gate-level simulation, synthesis, STA, ATPG, physical implementation, and silicon bring-up.</li><li>Support ATE pattern delivery, silicon debug, diagnostics, yield learning, and production test ramp.</li><li>Communicate DFT status, risks, trade-offs, and signoff readiness clearly with internal teams, external partners, vendors, and stakeholders.</li><li>Build scripts and automation to improve DFT implementation, reporting, pattern generation, and debug</li></ul>

<ul><li>7+ years of hands-on DFT experience in ASIC or SoC development.</li><li>Strong experience with scan insertion, ATPG, scan compression, fault simulation, and coverage closure.</li><li>Experience with MBIST, LBIST, JTAG, boundary scan, and test access architecture.</li><li>Strong understanding of scan shift/capture timing, at-speed testing, test-mode constraints, and multi-clock-domain DFT.</li><li>Experience debugging DFT issues across RTL, gate-level simulation, synthesis, STA, ATPG, and silicon bring-up.</li><li>Experience with complex SoC/IP integration, such as NoC, CPU, GPU/NPU, PCIe, Ethernet, UCIe, HBM/GDDR, or other high-speed interfaces.</li><li>Proficiency with industry-standard DFT tools such as Siemens Tessent, Synopsys TestMAX/DFT Compiler, Cadence Modus, or equivalent.</li><li>Strong scripting skills in Tcl, Python, Perl, or shell.</li><li>Excellent written and verbal communication skills, including the ability to work effectively with internal engineering teams, external partners, vendors, and cross-functional stakeholders.</li></ul>

<ul><li>Experience with AI accelerators, GPUs, NPUs, or highly parallel compute SoCs.</li><li>Experience with advanced-node, high-frequency, or high-density designs.</li><li>Experience with chiplets, multi-die systems, UCIe, 2.5D packaging, or package-aware test strategies.</li><li>Experience with HBM/GDDR or other high-bandwidth memory subsystem test requirements.</li><li>Experience with low-power DFT, UPF-aware test implementation, power domains, and power-aware ATPG.</li><li>Experience with silicon bring-up, ATE debug, diagnostics, yield ramp, and production test optimization.</li><li>Prior tapeout experience on advanced-node SoCs.</li></ul>

Preferred Qualifications (Nice to Have)

<ul><li>First silicon is testable, diagnosable, and ready for bring-up without major DFT workarounds.</li><li>DFT coverage targets are met across logic, memory, scan, and relevant fault models.</li><li>Test patterns are delivered on time with acceptable runtime, power, and ATE compatibility.</li><li>Physical design, timing, and manufacturing teams can close signoff without DFT-driven schedule risk.</li><li>Silicon debug and yield learning are accelerated through strong diagnostics and clear test visibility.</li></ul>

<p>Submit your application and show us how you think systematically about DFT architecture, coverage closure, silicon debug, and building testable silicon that scales.</p><p><em style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;margin:0px;padding:0px;"><i>Join us in our mission to democratize AI compute — where your DFT expertise helps turn advanced AI silicon into reliable, production-ready infrastructure.</i></em></p>

DFT Engineer

<p>We are a technology company focused on designing and developing advanced, customized server hardware solutions optimized for artificial intelligence workloads. Our mission is to accelerate AI innovation by delivering high-performance, scalable, and energy-efficient infrastructure for datacenter-scale inference.</p><p>Our chips in development are purpose-built for large-scale AI inference and will be deployed in rack-level systems where multiple devices collaborate to deliver optimal latency, throughput, and efficiency. We are building the next generation of AI infrastructure and are looking for engineers who deeply understand LLM inference servers, model execution runtimes, MoE inference, and distributed AI systems. This role is focused on integrating our AI accelerator platform as a backend into modern LLM inference servers such as vLLM, SGLang, TensorRT-LLM, or similar serving systems.</p><p>You will work on adding backend support for our hardware, enabling dense and MoE LLM inference, integrating custom operators and runtime paths, and optimizing the execution of large-scale models across NPU and heterogeneous NPU-GPU systems. You will work at the intersection of LLM serving, accelerator runtime, model execution, distributed inference, and hardware-software co-design.</p>

Description

<ul><li>Integrate our AI accelerator backend into LLM inference servers such as vLLM, SGLang, TensorRT-LLM, or similar frameworks.</li><li>Implement backend support for device registration, runtime execution, memory management, custom operators, and KV cache handling.</li><li> Enable dense and MoE LLM inference on our hardware, including attention execution, expert routing, expert execution, and distributed inference support.</li><li> Profile, debug, and optimize inference performance while building correctness, performance, and stress tests for NPU and heterogeneous NPU-GPU deployments.</li></ul>

<ul><li>5+ years of relevant experience with M.S./Ph.D. degree in CS/CE or equivalent experience.</li><li> Strong C/C++ and Python programming skills.</li><li>Hands-on experience modifying, extending, or contributing to any known LLM inference servers such as vLLM, SGLang, TensorRT-LLM etc.</li><li>Experience running and scaling workloads on large-scale, heterogeneous clusters (CPU + GPU) using distributed training or inference strategies.</li><li> Familiarity with PyTorch internals, custom op registration, tensor execution, model loading, and Hugging Face model integration.</li><li> Familiarity with distributed inference techniques such as tensor parallelism, expert parallelism, data parallelism, multi-device execution, and multi-node serving.</li></ul>

Requirements

<ul><li>Prior merged PRs or significant contributions to vLLM, SGLang, TensorRT-LLM or similar inference server repositories.</li><li>Strong knowledge of accelerator runtime and compiler stack.</li><li>Experience with GPU/NPU memory models, allocation, movement, and heterogeneous device execution.</li><li> Familiarity with distributed communication libraries such as NCCL, RCCL, oneCCL, MPI, UCX, or libfabric.</li><li> Experience with CUDA / Triton Kernels Experience</li></ul>

Nice to Have

<p><span style="background-color:rgb(255,255,255);color:rgb(0,0,0);font-family:Inter, &quot;Inter Fallback&quot;;"><span style="-webkit-text-stroke-width:0px;display:inline !important;float:none;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">This role is not for LLM deployment engineers who have only used inference servers to serve models or has written low-level kernels. We are also not looking for candidates whose experience is limited to running, configuring, or deploying models using vLLM, SGLang, TensorRT-LLM, or similar frameworks. We are looking for engineers who have worked on inference server internals. Are familiar with modifying the codebase, adding backend support, integrating custom operators, changing execution paths, or contributing to the framework itsel</span></span></p>

What We're Not Looking For

<ul><li>Work on cutting-edge AI hardware designed specifically for large-scale inference.</li><li>Build core inference server backend infrastructure for next-generation NPU and heterogeneous NPU-GPU systems.</li><li>Solve challenging problems at the intersection of LLM serving, AI accelerators, distributed runtime, MoE inference, and datacenter-</li></ul>

Why Join Us?

Inference Server Engineer

<div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;"><strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">Team:</strong> SoC Architecture – NPU Core &amp; ISA</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;"><strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">Type:</strong> Full-time – On-site</div>

Job Description

<p>We are a tech company specializing in the design and development of cutting-edge, customized server hardware solutions optimized for artificial intelligence and machine learning applications.</p><p>Our mission is to empower businesses and researchers to accelerate their AI initiatives by providing them with high-performance, scalable, and energy-efficient hardware infrastructure.</p>

<p><span style="background-color:rgb(255,255,255);color:rgb(0,0,0);font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;"><span style="-webkit-text-stroke-width:0px;display:inline !important;float:none;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">As a </span></span><strong style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:rgb(0, 0, 0);font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:bolder;letter-spacing:normal;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">RISC-V Architect</strong><span style="background-color:rgb(255,255,255);color:rgb(0,0,0);font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;"><span style="-webkit-text-stroke-width:0px;display:inline !important;float:none;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">, you will own the architecture of our AI Accelerator — a many-core RISC-V compute cluster. You will define the base ISA, the vector and matrix extensions, the per-core microarchitecture, and the cluster/NoC topology that turn real AI training and inference workloads into synthesizable, verification-ready RTL feeding our next-generation silicon. You set the architectural contracts that RTL, verification, toolchain, and compiler teams build against, and drive the integration and microarchitecture reviews that keep silicon faithful to the spec.</span></span></p>

<ul><li><strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">RISC-V core and ISA definition:</strong> define the base ISA, privilege modes, and scalar pipeline scope; specify the microarchitecture requirements that balance programmability, performance, and PPA.</li><li><strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">Vector and matrix extension architecture:</strong> own the RVV and AME matrix extensions — its register and accumulator model, instruction encodings in the custom-opcode space, and the golden-model semantics that define correct behavior.</li><li><strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">NoC and cluster architecture:</strong> design the on-chip interconnect — mesh topology, routing, flow control, virtual channels, the DMA/data-movement model, and how the cluster is represented to system software and the compiler.</li><li><strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">Memory and data-movement co-design:</strong> architect the per-core SRAM/scratchpad, DMA engines, and end-to-end data flows between local memory, the NoC, and the compute cores datapaths to sustain persistent throughput.</li><li><strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">Golden model and specification ownership:</strong> produce microarchitecture and AME specifications and interface contracts, and own the golden reference model's behavior, providing RTL, DV, and toolchain teams with one authoritative reference to build and verify against.</li><li><strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">Compiler and toolchain contracts:</strong> define the ISA/ABI and the intrinsic/builtin surface that the compiler backend and AME code generation target, collaborating with the toolchain team on autovectorization, tiling, and code-generation assumptions.</li><li><strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">Hands-on microarchitecture and integration:</strong> prototype and pressure-test critical blocks in SystemVerilog, and drive the integration and microarchitecture reviews across RTL, verification, compiler, performance, and physical-design teams to keep implementation faithful to the spec from ISA definition through to taped-out IP.</li></ul>

<ul><li>Bachelor's or Master's in Computer Engineering, Electrical Engineering, Computer Science, or related field.</li><li>10+ years in CPU, DSP, or NPU/accelerator IP architecture, with a proven track record of taking compute-core IP from ISA definition through RTL to silicon.</li><li>Deep expertise in the RISC-V architecture — the base ISA, privilege modes, and the practice of defining and extending ISAs with custom, non-standard instructions.</li><li>Hands-on experience with the RISC-V Vector extension (RVV) or matrix/tensor extensions (AME or equivalent AI matrix engines), including register models, instruction encodings, and datapath implications.</li><li>Strong grasp of NoC/interconnect architecture — mesh/torus topologies, routing, flow control, and virtual channels — with a clear feel for the latency, bandwidth, and area trade-offs of an implementation.</li><li>Solid microarchitecture skills: pipelines, memory hierarchy, DMA, coherency and memory ordering, and hazard handling, with the ability to reason quantitatively about PPA.</li><li>Solid understanding of AI workloads (GEMM, conv-as-GEMM, attention) and how they stress compute, memory, and interconnect.</li><li>Hands-on SystemVerilog experience — writing and reviewing synthesizable RTL and testbenches, co-simulating against a golden reference model, and driving coverage closure.</li><li>Proficiency in C/C++ and scripting (Python, Bash); comfort with instruction-set simulators, profilers, and performance modeling across the HW/SW boundary.</li><li>Excellent cross-functional communication and documentation skills; ability to write precise specifications and drive integration and microarchitecture reviews to architectural alignment with internal and external partners.</li></ul>

<ul><li>Direct experience with the RVV 1.0 and the emerging RISC-V Matrix (AMEX/IME) draft specifications, or active participation in a RISC-V working group.</li><li>Experience with a taped-out RISC-V core or contributions to open-hardware silicon.</li><li>Familiarity with MLIR/LLVM compiler stacks and graph-compilation flows (tiling, fusion, layout, quantization) for AI accelerators.</li><li>Hands-on with open-source RISC-V verification tooling (riscv-arch-test, riscv-dv, cocotb, Verilator) and formal methods.</li><li>Knowledge of chiplet/multi-die integration and NoC-to-AXI/CHI fabric bridging.</li><li>Experience with power/performance modeling and correlating pre-silicon models to silicon behavior.</li></ul>

Preferred Qualifications 

<ul><li>Own the architecture of a fully proprietary AI accelerator core — your ISA and microarchitecture decisions define silicon that we ship, not a derivative of someone else's IP.</li><li>Work at the frontier of RISC-V for AI: extend RVV and define a custom matrix engine on a fully open-source toolchain, alongside RTL, verification, compiler, and physical-design teams.</li><li>Build the compute foundation that feeds our next-generation accelerator tapeout, with hands-on impact from spec to silicon.</li><li>Competitive compensation, growth opportunities, and the chance to help define the platform that powers advanced AI workloads.</li></ul>

Why Join Us

<p>If you're passionate about architecting AI acceleration cores from the ISA up — turning AI workloads into custom vector and matrix silicon — we'd love to hear from you.</p><p>Apply now and help us deliver production</p>

Ready to Accelerate the Future of AI?

RISC-V/NPU Architect

<p>We are a tech company specializing in the design and development of cutting-edge, customized server hardware solutions optimized for artificial intelligence and machine learning applications. Our mission is to empower businesses and researchers to accelerate their AI initiatives by providing them with high-performance, scalable, and energy-efficient hardware infrastructure.</p><p>As a rapidly growing company at the forefront of AI hardware innovation, we are constantly seeking talented and motivated individuals to join our team. We offer a dynamic and challenging work environment, with opportunities to make a significant impact on the future of AI technology.</p>

<p><span style="background-color:rgb(255,255,255);color:rgb(0,0,0);font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;"><span style="-webkit-text-stroke-width:0px;display:inline !important;float:none;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">Compiler engineers, firmware &amp; driver engineers, hardware architects, ML framework engineers and performance &amp; validation teams</span></span></p>

<ul><li>The core runtime architecture that bridges the compiler and the hardware</li><li>Runtime execution engine performance and stability</li><li>Device memory management design and efficiency</li><li>Command submission and hardware interaction layer (in collaboration with firmware/driver teams)</li><li>Concurrency and scheduling model for model execution</li><li>Observability tooling (profiling, logging, tracing) within the runtime</li><li>Technical design decisions that ensure long-term scalability and maintainability</li></ul>

What You'll Own

<ul><li>5–8+ years of experience in systems software, runtime systems, or performance-critical infrastructure</li><li>Strong proficiency in <strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">C/C++</strong>and Python</li><li>Solid understanding of fundamentals of operating systems, multi-threading, synchronization, memory management, and cache behavior</li><li>Experience working close to hardware (GPU, accelerator, driver, or firmware environments)</li><li>Familiarity with command queues, execution engines, and DMA-based systems</li><li>Understanding of computational graphs, tensor execution, and memory layouts</li><li>Experience profiling and optimizing latency and throughput in performance-sensitive systems</li></ul>

<ul><li>Experience building or architecting a runtime from scratch</li><li>Familiarity with MLIR, LLVM, or compiler-runtime interfaces</li><li>Experience with one or many from CUDA, ROCm, TensorRT, TVM, XLA, ONNX Runtime or similar runtimes</li><li>Experience integrating custom hardware backends into PyTorch, ONNX or OpenXLA</li><li>Knowledge of quantization and mixed-precision inference</li><li>Experience with multi-device or distributed execution</li><li>Background in AI accelerator or semiconductor environments</li></ul>

<ul><li>You enable reliable end-to-end execution of compiled models on our NPU</li><li>Runtime overhead is minimal and performance targets are consistently met</li><li>Memory management and scheduling are efficient and scalable</li><li>The runtime architecture is robust, maintainable, and extensible</li><li>Compiler, firmware, and hardware teams can build confidently on top of your execution layer</li><li>The system supports real-world AI workloads with stability and observability</li></ul>

<p><em style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;"><i>Join us in our mission to democratize AI compute — where your firmware expertise becomes the bedrock of tomorrow's AI breakthroughs.</i></em></p>

Runtime Engineer (C/C++)

<p>We are a technology company focused on designing and developing advanced, customized server hardware solutions optimized for artificial intelligence workloads. Our mission is to accelerate AI innovation by delivering high-performance, scalable, and energy-efficient infrastructure for datacenter-scale inference. Our chips in development are purpose-built for large-scale AI inference and will be deployed in rack-level systems where multiple devices collaborate to deliver optimal latency, throughput, and efficiency. We are building the next generation of AI infrastructure and are looking for engineers who deeply understand high-performance networking, collective communication, and distributed AI systems.</p><p>&nbsp;<br>This role is focused on designing and implementing collective communication support for our AI accelerator platform, including both NPU-native communication and heterogeneous NPU-GPU communication. You will work at the intersection of accelerator runtime, networking, distributed AI workloads, and hardware-software co-design.</p>

<p>• Design and implement collective communication primitives for AI accelerators.</p><p>• Build NPU-native CCL support for multi-chip and rack-scale AI inference systems.</p><p>• Design and implement heterogeneous NPU-GPU communication paths for distributed AI workloads.</p><p>• Develop communication runtime components for device discovery, rank management, topology awareness, stream/queue integration, events, and synchronization.</p><p>• Work on transport-layer integration across PCIe, Ethernet/RDMA, custom accelerator fabrics, or other device-to-device communication mechanisms.</p><p>• Collaborate with hardware, runtime, compiler, and model-serving teams to co-design scalable communication paths for AI workloads.</p><p>• Profile, debug, and optimize communication bottlenecks including bandwidth, latency, congestion, synchronization overhead, and compute-communication overlap.</p><p>• Build correctness, performance, and stress tests for multi-device and heterogeneous communication scenarios.Requirements</p><p>• 5+ years of relevant experience with M.S./Ph.D. degree in CS/CE or equivalent experience.</p><p>• Strong C/C++ and python programming skills with experience building low-level runtime, driver, networking, or distributed systems software.</p><p>• Deep understanding of collective communication primitives such as AllReduce, ReduceScatter, AllGather, AllToAll, Broadcast, Send/Recv, and Barrier.</p><p>• Familiarity with any networking and distributed communication libraries such as NCCL, RCCL, oneCCL, MPI, UCX, or libfabric.</p><p>• Strong knowledge of GPU/NPU memory models, accelerator memory allocation, memory registration, peer-to-peer transfers, and heterogeneous device communication.</p><p>• Experience with accelerator runtime concepts such as queues, streams, events, command submission, completion handling, synchronization, and memory management.</p><p>• Strong understanding of hardware-software interaction in accelerator systems, including DMA engines, device memory, interrupts, doorbells, fences, and completion signaling.</p><p>• Knowledge of high-performance networking like InfiniBand, and RoCE.</p><p>• Ability to work close to hardware, including DMA engines, queues, streams, fences, completion signaling, NoC/fabric behavior, and accelerator runtime integration.</p><p>• Strong performance engineering skills for optimizing bandwidth, latency, synchronization overhead, congestion, and compute-communication overlap.</p>

<p>Familiarity with PyTorch distributed backends, custom ProcessGroup implementations, or distributed framework integration.</p><p>• Experience optimizing communication for LLM workloads, including tensor parallelism, MoE expert parallelism, KV-cache transfer, or disaggregated inference.</p><p>• Experience integrating communication backends with distributed AI frameworks or serving systems such as PyTorch distributed, vLLM, SGLang, or similar platforms.</p>

<p><span style="background-color:rgb(255,255,255);color:rgb(0,0,0);font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;"><span style="-webkit-text-stroke-width:0px;display:inline !important;float:none;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">This role is not focused on general backend networking, web services, prompt engineering, or application-layer GenAI development. Instead, it is centered on low-level collective communication, accelerator runtime, heterogeneous device communication, and distributed AI performance at scale.</span></span></p>

<div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">Work on cutting-edge AI hardware designed specifically for large-scale inference</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Build core communication infrastructure for next-generation NPU and heterogeneous NPU-GPU systems.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Solve challenging problems at the intersection of AI accelerators, networking, distributed runtime, and datacenter-scale systems.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Collaborate with hardware, compiler, runtime, and model-serving teams on a full-stack AI infrastructure platform.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Make a direct impact on the scalability</div>

Network CCL Engineer

<p>We are a technology company focused on designing and developing advanced, customized server hardware solutions optimized for artificial intelligence workloads. Our mission is to accelerate AI innovation by delivering high-performance, scalable, and energy-efficient infrastructure for datacenter-scale inference.&nbsp;</p><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">Our chips in development are purpose-built for large-scale AI inference and will be deployed in rack-level systems where multiple devices collaborate to deliver optimal latency, throughput, and efficiency. We are building the next generation of AI infrastructure and are looking for engineers who deeply understand how modern large language models behave at scale.&nbsp;</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">&nbsp;</div><p>This role is focused on LLM systems, architecture, and performance. You will work at the intersection of model internals and hardware, ensuring that state-of-the-art models run efficiently on our platform.&nbsp;</p>

<ul><li>Analyze, profile and optimize large language model (LLM) inference performance across distributed, multi-chip systems </li><li>Bring a deep understanding of transformer architectures, including dense and Mixture-of-Experts (MoE) models </li><li>Evaluate and benchmark different LLMs (e.g., LLaMA, Mistral, Qwen, DeepSeek) on custom hardware </li><li>Design and implement optimizations for attention mechanisms (e.g., Flash Attention, grouped-query attention, sliding window attention) </li><li>Work on model-level optimizations such as quantization (INT8/FP8), KV-cache management, batching, and parallelism strategies </li><li>Collaborate with hardware and compiler teams to co-design efficient inference pipelines </li><li>Build and maintain benchmarking frameworks to evaluate latency, throughput, and scaling behavior </li><li>Analyze trade-offs between model architecture choices and system-level performance </li><li>Contribute to model deployment strategies for large-scale datacenter environments </li><li>Stay up to date with the latest research in LLM architectures and inference optimization&nbsp;</li></ul>

<ul><li>Strong understanding of transformer architectures and LLM internals </li><li>Hands-on experience working with multiple modern LLMs (e.g., LLaMA, Mistral, Qwen, DeepSeek, etc.) </li><li>Deep knowledge of different LLM architectures such as dense models and Mixture-of-Experts (MoE) architectures </li><li>Familiarity with attention mechanisms and their optimizations </li><li>Experience with LLM inference optimization techniques (quantization, pruning, KV caching, batching, etc.) </li><li>Strong Python skills and experience with ML frameworks (PyTorch, JAX, or similar) </li><li>Experience with distributed systems and large-scale inference workloads </li><li>Ability to profile and debug performance bottlenecks across hardware and software stacks </li><li>Strong systems thinking and ability to work across model, runtime, and hardware layers&nbsp;</li><li>&nbsp;</li></ul>

Requirements 

<ul><li>8+ years of relevant experience in deep learning, AI systems, or performance engineering </li><li>Experience working close to hardware (GPU, TPU, or custom accelerators) </li><li>Experience with parallelism strategies (tensor parallelism, pipeline parallelism, expert parallelism) </li><li>Familiarity with datacenter-scale deployment, orchestration and inference servers (e.g., vLLM) </li><li>Background in performance engineering or systems optimization&nbsp;</li></ul>

<p><span style="background-color:rgb(255,255,255);color:rgb(0,0,0);font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;"><span style="-webkit-text-stroke-width:0px;display:inline !important;float:none;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">This role is </span></span><strong style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:rgb(0, 0, 0);font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:bolder;letter-spacing:normal;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">not focused on prompt engineering, or application-layer GenAI development</strong><span style="background-color:rgb(255,255,255);color:rgb(0,0,0);font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;"><span style="-webkit-text-stroke-width:0px;display:inline !important;float:none;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">. Instead, it is centered on </span></span><strong style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:rgb(0, 0, 0);font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:bolder;letter-spacing:normal;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">deep LLM internals, architecture, and inference performance at scale</strong><span style="background-color:rgb(255,255,255);color:rgb(0,0,0);font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;"><span style="-webkit-text-stroke-width:0px;display:inline !important;float:none;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">.&nbsp;</span></span></p>

What We’re Not Looking For

<ul><li>Work on cutting-edge AI hardware designed specifically for LLM inference </li><li>Solve challenging problems at the intersection of AI models and systems </li><li>Collaborate with a team pushing the boundaries of datacenter-scale AI performance </li><li>Make a direct impact on the future of AI infrastructure&nbsp;</li></ul>

Senior AI Engineer – LLM Systems

<div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;"><strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">Employment Type:</strong>Full-time</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;"><strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">Reports to:</strong>CEO</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;"><strong style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;font-weight:bolder;margin:0px;padding:0px;">Group Operations: </strong>UAE · Greece ·<span style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;margin:0px;padding:0px;" lang="EN-US">India</span></div>

<p>We are a technology company building advanced AI infrastructure, networking, and telecom software, with a portfolio spanning open network operating systems and AI data center solutions. Headquartered in Dubai Internet City with operations across the UAE, Greece, and<span style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;margin:0px;padding:0px;" lang="EN-US"> India</span>, we serve telecom operators, enterprises, and service providers across the GCC, APAC, and EMEA, and work closely with global hardware and technology partners.</p><p>As we scale internationally, we are hiring our first dedicated in-house lawyer to own the commercial-legal function end-to-end. This is a hands-on, generalist role for someone comfortable being the sole legal operator in a fast-moving technology company — building processes from scratch, partnering directly with business teams, and knowing when to escalate specialist or contentious matters to external counsel.</p>

<p><span style="background-color:rgb(255,255,255);color:rgb(0,0,0);font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;"><span style="-webkit-text-stroke-width:0px;display:inline !important;float:none;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">The Legal Business Partner will take primary ownership of contract law and intellectual property protection across our multi-jurisdictional operations, with a working-level responsibility for compliance. The focus is on enabling the business: closing deals, protecting our core software and hardware IP, and keeping the company on the right side of the regulations that govern cross-border AI and networking technology.</span></span></p>

Role Summary

<p>Create contract playbooks, templates, and approval workflows.<br>Draft, review, and track renewals across the full contract set: Master Services Agreements (MSAs), NDAs, outsourcing / out-staffing contracts, license agreements, and other commercial contracts.<br>Maintain a centralized contract register, including key dates, obligations, and renewal terms.<br>Align contract terms with business objectives, partnering closely with sales, product, and leadership.<br>Support due diligence procedures (investor, customer, and partner-driven).<br>Identify, assess, and mitigate legal and commercial risks in contracts, including IP, liability, indemnification, warranty, and data protection clauses.<br>Ensure contracts comply with applicable UAE law (including free zone / DIC regulations) and relevant international regulations (export control, data privacy, telecom regulatory requirements) across our multi-jurisdictional operations.</p>

Contract Law (Core Responsibility)

<ul style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:rgb(0, 0, 0);display:block;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;list-style-type:disc;list-style:disc;margin-block:1em;margin-bottom:0px;margin-inline:0px;margin-right:0px;margin-top:0px;orphans:2;padding-inline-start:40px;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;" type="disc"><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Implement multi-jurisdictional IP &amp; IT legal and privacy frameworks.</p></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Strengthen robust IP assignment clauses in employee and contractor agreements across all three jurisdictions (UAE, Greece, Singapore).</p></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Support the establishment of legal guardrails for data use, content ownership, privacy, and IP risk mitigation.</p></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Manage trademark, patent, and software copyright registrations, and the domain portfolio.</p></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Lead open-source license review and compliance: legal review of open-source components adopted into products (including copyleft / GPL implications for distributed firmware and drivers), maintenance of a license inventory (SBOM), and fulfillment of attribution and source-code obligations — including what employees may contribute upstream and under what CLA.</p></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Conduct patent clearance for in-house developments: freedom-to-operate analyses and prior-art searches in target markets to confirm our developments do not infringe third-party patents, plus ongoing monitoring of competitor patent filings.</p></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Support invention disclosure and filing: patentability assessment of internal inventions and coordination of the patent filing strategy aligned with the product roadmap.</p></li></ul>

Intellectual Property (Core Responsibility)

<div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;"><em style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;margin:0px;padding:0px;"><i>Expected at a base level; specialist and contentious matters supported by external counsel.</i></em></div><ul style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:rgb(0, 0, 0);display:block;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;list-style-type:disc;list-style:disc;margin-block:1em;margin-bottom:0px;margin-inline:0px;margin-right:0px;margin-top:0px;orphans:2;padding-inline-start:40px;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;" type="disc"><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Run periodic sanctions and export-control screening.</p></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Track regulatory filings.</p></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Track telecom regulatory developments in relevant markets.</p></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Organize the handling of personal data in line with the UAE Personal Data Protection Law (PDPL) and GDPR.</p></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Support employment compliance (ongoing adherence to UAE Labour Law and free zone employment rules).</p></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Support product export-control compliance: classification against control lists (US EAR / ECCN, EU dual-use), spec adjustments to stay within permitted thresholds, and tracking of regulatory updates.</p></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Support multi-regional EDA and IP license compliance: territorial / user-access restrictions, re-export limits, and deemed-export controls for engineer access across jurisdictions and external design partners.</p></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Support end-user / end-use verification for customer shipments and technology transfers.<em style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;margin:0px;padding:0px;"><i>Expected at a base level; specialist and contentious matters supported by external counsel.</i></em></p></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Run periodic sanctions and export-control screening.</p></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Track regulatory filings.</p></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Track telecom regulatory developments in relevant markets.</p></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Organize the handling of personal data in line with the UAE Personal Data Protection Law (PDPL) and GDPR.</p></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Support employment compliance (ongoing adherence to UAE Labour Law and free zone employment rules).</p></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Support product export-control compliance: classification against control lists (US EAR / ECCN, EU dual-use), spec adjustments to stay within permitted thresholds, and tracking of regulatory updates.</p></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Support multi-regional EDA and IP license compliance: territorial / user-access restrictions, re-export limits, and deemed-export controls for engineer access across jurisdictions and external design partners.</p></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Support end-user / end-use verification for customer shipments and technology transfers.</p></li></ul>

Compliance (Working Level — Nice to Have)

<ul style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:rgb(0, 0, 0);display:block;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;list-style-type:disc;list-style:disc;margin-block:1em;margin-bottom:0px;margin-inline:0px;margin-right:0px;margin-top:0px;orphans:2;padding-inline-start:40px;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;" type="disc"><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Law degree (LLB / JD or equivalent) and qualification in a recognized jurisdiction.</p></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">3–6 years of post-qualification experience in commercial / contracts law, ideally combining law-firm and in-house experience.</p></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Strong drafting and negotiation skills across MSAs, NDAs, licensing, and outsourcing / commercial agreements.</p></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Working knowledge of UAE commercial law and free zone regulations; comfort operating across multiple jurisdictions.</p></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Solid grounding in IP protection for software and technology companies, including IP assignment, licensing, and open-source considerations.</p></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Practical familiarity with data protection regimes (UAE PDPL, GDPR).</p></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Fluent English (written and verbal).</p></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Self-directed and pragmatic — able to build processes from scratch, prioritize commercial outcomes, and manage external counsel effectively.</p></li></ul>

<ul style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:rgb(0, 0, 0);display:block;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;list-style-type:disc;list-style:disc;margin-block:1em;margin-bottom:0px;margin-inline:0px;margin-right:0px;margin-top:0px;orphans:2;padding-inline-start:40px;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;" type="disc"><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Prior in-house experience at a networking, telecom, semiconductor, software, or AI infrastructure company.</p></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Exposure to export control and dual-use regimes (US EAR, EU dual-use).</p></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Experience with open-source governance and SBOM management.</p></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Familiarity with patent processes (FTO analysis, invention disclosure, filing coordination).</p></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Arabic and/or Greek language skills, given group operations in the UAE and Greece.</p></li></ul>

<ul style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:rgb(0, 0, 0);display:block;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;list-style-type:disc;list-style:disc;margin-block:1em;margin-bottom:0px;margin-inline:0px;margin-right:0px;margin-top:0px;orphans:2;padding-inline-start:40px;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;" type="disc"><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Own the legal function end-to-end at a fast-scaling AI infrastructure company.</p></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Work at the intersection of cutting-edge technology, cross-border commerce, and complex IP.</p></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Partner directly with founders and business leaders, with real influence over how deals get done.</p></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><p style="margin-left:0px;">Shape the legal foundation of a company operating across three regions and global markets.</p></li></ul>

Legal Business Partner (In-House Counsel)

<p><span style="background-color:rgb(255,255,255);color:rgb(0,0,0);font-family:Inter, &quot;Inter Fallback&quot;;font-size:18px;"><span style="-webkit-text-stroke-width:0px;display:inline !important;float:none;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">&nbsp;</span></span><span style="background-color:rgb(255,255,255);color:rgb(0,0,0);font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;"><span style="-webkit-text-stroke-width:0px;display:inline !important;float:none;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">Silicon, firmware, runtime, datacenter-software and architecture teams to build a mlir-compiler and software stack that brings next-gen AI/NPU hardware into modern datacenter environments and production AI workloads</span></span></p>

<ul style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:rgb(3, 7, 17);display:block;font-family:Inter, &quot;Inter Fallback&quot;;font-size:medium;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;list-style:disc;margin-block:1em;margin-bottom:0px;margin-inline:0px;margin-right:0px;margin-top:0px;orphans:2;padding-inline-start:40px;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;"><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;">Define and implement MLIR dialects and lowering pipelines targeting our AI-accelerator/NPU platform.</li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;">Lower ML graphs (e.g., from ONNX/PyTorch) into optimized kernels focusing on fusion, tiling and vectorization.</li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;">Profile, benchmark and optimize compiler output to meet latency, throughput and power targets.</li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;">Work with hardware architects and runtime/framework teams to co-design compiler features.</li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;">Build a future‐ready, portable compiler stack that supports multiple hardware generations.</li></ul>

<ul style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:rgb(3, 7, 17);display:block;font-family:Inter, &quot;Inter Fallback&quot;;font-size:medium;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;list-style:disc;margin-block:1em;margin-bottom:0px;margin-inline:0px;margin-right:0px;margin-top:0px;orphans:2;padding-inline-start:40px;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;"><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><div style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-size:0.8125rem;line-height:1.5;margin:0px;padding:0px;">5+ years of experience in compiler engineering or high‐performance systems.</div></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><div style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-size:0.8125rem;line-height:1.5;margin:0px;padding:0px;">Strong programming skills in C++ (modern standards), and scripting or tooling in Python.</div></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><div style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-size:0.8125rem;line-height:1.5;margin:0px;padding:0px;">Hands-on experience with MLIR and/or LLVM (designing/extending dialects, lowering, optimization).</div></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><div style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-size:0.8125rem;line-height:1.5;margin:0px;padding:0px;">Deep understanding of compiler internals: IRs, code scheduling, vectorization, loop transformations.</div></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><div style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-size:0.8125rem;line-height:1.5;margin:0px;padding:0px;">Strong familiarity with AI/ML frameworks (e.g.,PyTorch, ONNX, TensorFlow).</div></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><div style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-size:0.8125rem;line-height:1.5;margin:0px;padding:0px;">Excellent understanding of ML operations such as tensor operators, matmuls, quantization, dynamic shapes.</div></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><div style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-size:0.8125rem;line-height:1.5;margin:0px;padding:0px;">Robust understanding of computer architecture and memory hierarchy.</div></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;">Bachelor’s (or higher) degree in Computer Science, Computer Engineering or equivalent</li></ul>

<ul style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:rgb(3, 7, 17);display:block;font-family:Inter, &quot;Inter Fallback&quot;;font-size:medium;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;list-style:disc;margin-block:1em;margin-bottom:0px;margin-inline:0px;margin-right:0px;margin-top:0px;orphans:2;padding-inline-start:40px;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;"><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><div style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-size:0.8125rem;line-height:1.5;margin:0px;padding:0px;">Prior experience targeting NPU/AI accelerator hardware.</div></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><div style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-size:0.8125rem;line-height:1.5;margin:0px;padding:0px;">Contributions to open‐source compiler projects (MLIR, LLVM,Torch-MLIR, ONNX-MLIR).</div></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><div style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-size:0.8125rem;line-height:1.5;margin:0px;padding:0px;">Familiarity with runtime systems, scheduling, resource sharing, memory movement engines and, interconnects.</div></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><div style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-size:0.8125rem;line-height:1.5;margin:0px;padding:0px;">Previous leadership role driving compiler architecture, setting standards, mentoring teams and owning roadmap.</div></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><div style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-size:0.8125rem;line-height:1.5;margin:0px;padding:0px;">Familiarity with software development tooling: Git, CI/CD, debuggers, profilers.</div></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;">Advanced degree (M.S./Ph.D.) preferred.</li></ul>

<ul style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:rgb(3, 7, 17);display:block;font-family:Inter, &quot;Inter Fallback&quot;;font-size:medium;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;list-style:disc;margin-block:1em;margin-bottom:0px;margin-inline:0px;margin-right:0px;margin-top:0px;orphans:2;padding-inline-start:40px;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;"><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><div style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-size:0.8125rem;line-height:1.5;margin:0px;padding:0px;">A production compiler IR/dialect is designed and integrated, successfully lowering key ML workloads to the target NPU.</div></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><div style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-size:0.8125rem;line-height:1.5;margin:0px;padding:0px;">Key operator kernels (matmul, convolution, etc) show measurable performance gains (reduced latency, increased throughput) on the hardware or simulator.</div></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><div style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-size:0.8125rem;line-height:1.5;margin:0px;padding:0px;">The compiler pipeline handles multi‐die/chiplet topology correctly and efficiently schedules across devices.</div></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><div style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-size:0.8125rem;line-height:1.5;margin:0px;padding:0px;">Runtime interfaces and resource scheduling between host and accelerator are functional and validated with real workloads.</div></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><div style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-size:0.8125rem;line-height:1.5;margin:0px;padding:0px;">Telemetry/debug hooks and performance counters from compiled code are available and used for performance analysis by other teams.</div></li><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;">The architecture and roadmap for next-gen hardware are defined, and junior engineers are actively mentored within the compiler team.</li></ul>

What Success Looks Like (First 6–9 Months)

<div class="description-container wrap-break-word" style="--tw-space-y-reverse:0;-webkit-text-stroke-width:0px;border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:rgb(3, 7, 17);font-family:Inter, &quot;Inter Fallback&quot;;font-size:medium;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;margin-block:0px 16px;margin:0px;orphans:2;overflow-wrap:break-word;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;"><div class="styled-div" style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;margin:0px;padding:0px;" data-testid="job-description"><ul style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;display:block;list-style:disc;margin-block:1em;margin-bottom:0px;margin-inline:0px;margin-right:0px;margin-top:0px;padding-inline-start:40px;padding:0px;"><li style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;display:list-item;font-size:0.8125rem;line-height:1.5;margin-bottom:0px;margin-right:0px;margin-top:0px;padding:0px;text-align:-webkit-match-parent;"><div style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-size:0.8125rem;line-height:1.5;margin:0px;padding:0px;"><div style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-size:0.8125rem;line-height:1.5;margin:0px;padding:0px;"><p><em style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;margin:0px;padding:0px;"><i>Join us in our mission to democratize AI compute — where your firmware expertise becomes the&nbsp;</i></em></p><div style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-size:0.8125rem;line-height:1.5;margin:0px;padding:0px;"><em style="border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;margin:0px;padding:0px;"><i>bedrock of tomorrow's AI breakthroughs.</i></em></div></div></div></li></ul></div></div><div class="flex flex-col items-center gap-y-4" style="--tw-space-y-reverse:0;-webkit-text-stroke-width:0px;align-items:center;border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:rgb(3, 7, 17);display:flex;flex-direction:column;font-family:Inter, &quot;Inter Fallback&quot;;font-size:medium;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;margin-block:0px 16px;margin:0px;orphans:2;padding:0px;row-gap:16px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;"><div class="flex items-center gap-x-4" style="align-items:center;border:0px solid rgb(229, 231, 235);box-sizing:border-box;column-gap:16px;display:flex;margin:0px;padding:0px;">&nbsp;</div></div><p><br>&nbsp;</p>

Compiler Engineer

<div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">Location: Dubai - UAE</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">Team: Hardware Engineering – Package Design &amp; Bring-Up</div><p>Type: Full-time – On-site</p>

<p><span style="background-color:rgb(255,255,255);color:rgb(0,0,0);font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;"><span style="-webkit-text-stroke-width:0px;display:inline !important;float:none;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">We are a tech company specializing in the design and development of cutting-edge, customized&nbsp;server hardware solutions optimized for artificial intelligence and machine learning applications.&nbsp;Our mission is to empower businesses and researchers to accelerate their AI initiatives by&nbsp;providing them with high-performance, scalable, and energy-efficient hardware infrastructure.&nbsp;As a rapidly growing company at the forefront of AI hardware innovation, we are constantly&nbsp;seeking talented and motivated individuals to join our team. We offer a dynamic and challenging&nbsp;work environment, with opportunities to make a significant impact on the future of AI technology.</span></span></p>

<p><span style="background-color:rgb(255,255,255);color:rgb(0,0,0);font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;"><span style="-webkit-text-stroke-width:0px;display:inline !important;float:none;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">As a Package Design Engineer, you will own the chip package of our AI accelerators end to&nbsp;end, from packaging technology selection and die/package/board co-design through substrate&nbsp;and interposer design, package-level test, and first-silicon bring-up. You will turn multi-chiplet&nbsp;silicon with demanding high-speed interfaces into robust, manufacturable, high-performance&nbsp;packages, working at the intersection of silicon design, signal and power integrity, thermal-mechanical engineering, and the foundry/OSAT supply chain.</span></span></p>

<div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Package architecture and technology selection: evaluate standard flip-chip BGA and&nbsp;advanced packaging options (2.5D silicon interposer, silicon bridge, fan-out, 3D&nbsp;stacking) against product requirements, and drive die/package/board co-optimization of&nbsp;floorplans, bump patterns, pad rings, and ball-out with silicon and system teams.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Multi-chiplet package design: own substrate and interposer design for multi-die&nbsp;assemblies, including netlist management, routing, layer stack-up definition, and design-rule compliance across compute, memory, and I/O chiplets.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• High-speed interface packaging: deliver package channels that meet the budgets of&nbsp;PCIe Gen5/Gen6, 400/800G Ethernet (56G/112G PAM4 SerDes), HBM, and UCIe/BoW&nbsp;die-to-die links, collaborating with signal and power integrity engineers on extraction,&nbsp;simulation, and margin sign-off.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Power, thermal, and mechanical co-design: define the package PDN, decoupling&nbsp;strategy, and thermal solution for high-power accelerator silicon, and manage warpage,&nbsp;CTE mismatch, and reliability risks together with thermal-mechanical engineers.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Manufacturing and supply-chain execution: engage foundries, OSATs, and substrate&nbsp;suppliers on design rules, DFM feedback, assembly flows, qualification, and yield&nbsp;improvement, and drive package NPI from tape-out to production release.<br>• Package test and silicon bring-up: define package-level test and characterization&nbsp;plans, support first-silicon bring-up in the lab, and lead package-related debug and&nbsp;failure analysis through to root cause and corrective action.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Cross-functional collaboration and documentation: write clear package&nbsp;specifications, design guidelines, and review material, and lead design reviews with&nbsp;silicon, board, SI/PI, thermal, and product engineering teams.</div>

<div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Bachelor’s or Master’s in Electrical Engineering, Materials Science, Mechanical&nbsp;Engineering, or related field.&nbsp;</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• 8+ years in semiconductor package design, with a strong focus on high-performance&nbsp;digital ASICs, GPUs, or AI accelerators.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Proven track record of taking complex multi-chiplet packages (2.5D interposer, silicon&nbsp;bridge, or fan-out based) from concept to production.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Hands-on experience with both standard flip-chip BGA and advanced packaging&nbsp;technologies such as CoWoS, EMIB, InFO/FoCoS, or equivalent foundry and OSAT&nbsp;platforms.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Package design experience for high-speed serial interfaces, specifically PCIe&nbsp;Gen5/Gen6 and 400/800G Ethernet, including breakout, escape routing, and channel&nbsp;budget ownership.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Experience with die-to-die interconnects such as UCIe or Bunch of Wires (BoW),&nbsp;including bump map definition, channel design, and routing rules for D2D links.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Experience integrating HBM or similar memory subsystems on interposer or bridge,&nbsp;including routing, stack-up, and assembly considerations.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Solid grounding in package signal and power integrity, transmission line theory, and&nbsp;PDN design, with the ability to drive and interpret extraction and simulation results.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Working knowledge of thermal and mechanical fundamentals for large-body, high-power&nbsp;packages, including warpage control and JEDEC reliability qualification.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Experience supporting package test, characterization, first-silicon bring-up, and failure&nbsp;analysis in collaboration with test and product engineering.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Proficiency with package EDA tools such as Cadence APD/SiP Layout or Synopsys&nbsp;3DIC Compiler, plus familiarity with SI/PI analysis tools (Ansys HFSS/SIwave, Cadence&nbsp;Clarity/Sigrity, or similar).</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Excellent cross-functional communication and documentation skills, including experience&nbsp;working directly with foundry, OSAT, and substrate vendor engineering teams.&nbsp;</div>

<div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Experience with 3D stacking and hybrid bonding technologies (SoIC, Foveros, or similar)&nbsp;and their design and test implications.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Exposure to co-packaged optics or photonics packaging for high-bandwidth I/O.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Experience defining packaging testchips and running technology qualification vehicles&nbsp;with foundry or OSAT partners.<br>• Hands-on use of thermal and mechanical simulation tools (Ansys Icepak, Celsius,&nbsp;mechanical FEA) for package-level analysis.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Familiarity with UCIe compliance and interoperability testing, or participation in chiplet&nbsp;standards bodies (UCIe Consortium, OCP ODSA).</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Experience managing OSAT and substrate vendor relationships, schedules, and cost&nbsp;trade-offs during NPI.<br>&nbsp;</div>

<div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Own the package of a next-generation AI accelerator from first concept to working&nbsp;silicon, where your decisions directly set the product’s performance, power, and cost.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Work in a tight cross-functional team of silicon, board, SI/PI, and thermal engineers that&nbsp;values technical depth and hands-on problem solving.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Cover the full scope in one role: architecture, design, supplier engagement, lab bring-up,&nbsp;and production ramp.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Competitive compensation, growth opportunities, and the chance to help define the&nbsp;platform that powers advanced AI workloads.</div>

<div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">f you’re passionate about turning multi-chiplet silicon into robust, high-performance packages</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">— we’d love to hear from you.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">Apply now and help us deliver production-ready platforms that make AI faster, safer, and more</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">efficient.</div>

Package Design Engineer

<div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">Location: Dubai - UAE</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">Team: Hardware Engineering – Board Design &amp; Bring-Up</div><p>Type: Full-time – On-site</p>

<div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">We are a tech company specializing in the design and development of cutting-edge, customized&nbsp;server hardware solutions optimized for artificial intelligence and machine learning applications.&nbsp;Our mission is to empower businesses and researchers to accelerate their AI initiatives by&nbsp;providing them with high-performance, scalable, and energy-efficient hardware infrastructure.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">As a rapidly growing company at the forefront of AI hardware innovation, we are constantly&nbsp;seeking talented and motivated individuals to join our team. We offer a dynamic and challenging&nbsp;work environment, with opportunities to make a significant impact on the future of AI technolo</div>

<p><span style="background-color:rgb(255,255,255);color:rgb(0,0,0);font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;"><span style="-webkit-text-stroke-width:0px;display:inline !important;float:none;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">As a Staff Hardware Board Design Engineer, you will be the electrical design authority for the&nbsp;boards that carry our AI accelerator silicon, from the first test PCB that powers up a new chip to&nbsp;the production accelerator card or module that ships in a data center rack. You will set board-level architecture, translate silicon and system requirements into schematics, power trees, and&nbsp;high-speed interface budgets, define the constraints that drive layout, and take the resulting&nbsp;hardware through lab bring-up, characterization, and debug. You will own board programs end&nbsp;to end and be the person the silicon, firmware, and validation teams come to when the platform&nbsp;has to work.</span></span></p>

<div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Accelerator board architecture and schematic design: set board-level architecture&nbsp;and own schematic capture for AI accelerator cards, modules, and system boards,&nbsp;including component selection, clocking and reset topologies, sideband management&nbsp;interfaces, and connector and form-factor decisions.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Test PCB design for silicon bring-up: design the evaluation, characterization, and&nbsp;socketed test boards used to power up and qualify new chips, providing programmable&nbsp;rails and current sensing, clean clock sources, JTAG and scan access, probe and&nbsp;instrumentation points, thermal fixturing, and package breakout structures that make first&nbsp;silicon observable and debuggable.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Power delivery network design: design high-current, multi-rail power trees for&nbsp;accelerator-class devices, covering multi-phase VRM selection and compensation, PDN&nbsp;impedance targets, decoupling strategy, power sequencing and telemetry over PMBus,&nbsp;and protection and hot-swap behaviour.• High-speed interface budgets and layout direction: define stackup, material,&nbsp;impedance, and routing constraints for PCIe Gen5 and Gen6, DDR5, LPDDR5, GDDR6&nbsp;and GDDR7 or HBM-adjacent interfaces, 100G to 800G Ethernet, and die-to-die and&nbsp;SerDes links, then drive layout execution with our in-house PCB layout and signal and&nbsp;power integrity engineers as well as external layout partners.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Lab bring-up, characterization, and debug: plan and execute board and silicon bring-&nbsp;up, run electrical characterization and margining, and root-cause failures across the&nbsp;hardware, firmware, and silicon boundary using oscilloscopes, high-bandwidth probes,&nbsp;BERTs, VNAs, protocol and power analyzers, and thermal imaging.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Manufacturing readiness and vendor execution: drive DFM, DFT, and DFA reviews,&nbsp;prototype and NPI builds, ECO and BOM management, and compliance activities with&nbsp;fabricators, assembly houses, ODMs, and contract manufacturers through to volume&nbsp;production.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Technical leadership and documentation: write board specifications, schematic&nbsp;review packages, bring-up and test plans, and errata, act as design authority in reviews,&nbsp;align silicon, package, firmware, thermal, mechanical, and validation teams around a&nbsp;single platform definition, and mentor engineers as the board team grows.</div>

<div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Bachelor’s or Master’s in Electrical Engineering, Electronics Engineering, or related field.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• 10+ years of board-level hardware design experience with a strong focus on high-speed&nbsp;digital boards for compute, networking, or accelerator products, including at least one&nbsp;platform owned end to end from concept through volume production and at least one&nbsp;first-silicon bring-up.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Proven ownership of schematic capture and board architecture in a professional ECAD&nbsp;flow such as Cadence Allegro System Capture, OrCAD Capture, or Altium Designer.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Hands-on experience designing and debugging high-speed interfaces such as PCIe&nbsp;Gen4 or newer, DDR4 or DDR5, LPDDR, GDDR, or multi-gigabit SerDes and Ethernet&nbsp;links, including how loss, crosstalk, and return-path decisions shape the schematic and&nbsp;stackup.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Strong power electronics competence at board level: multi-phase VRM design, high-&nbsp;current PDN design, decoupling and target impedance analysis, power sequencing, and&nbsp;telemetry.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Demonstrated silicon or board bring-up experience: taking untested hardware from first&nbsp;power-on to functional and characterized, and driving issues to root cause.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Fluency with lab instrumentation and measurement practice, including oscilloscopes and&nbsp;probing technique, power and network analyzers, and protocol or bus analyzers.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Working knowledge of low-speed management and control subsystems: I2C, SMBus,&nbsp;SPI, UART, JTAG, EEPROM and FRU handling, BMC or MCU based board&nbsp;management, and reset and sequencing logic.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Practical command of DFM, DFT, and DFA, PCB fabrication and assembly processes,&nbsp;and design release packages, with experience working directly with fab and assembly&nbsp;vendors.<br>• Proficiency with Python or equivalent scripting for lab automation, data capture, and&nbsp;measurement post-processing.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Demonstrated technical leadership: acting as design authority in schematic and layout&nbsp;reviews, steering external layout houses, ODMs, and component vendors, and&nbsp;mentoring less experienced engineers.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Excellent cross-functional communication and documentation skills, with the ability to&nbsp;lead design reviews and to drive alignment with silicon, firmware, mechanical, and&nbsp;manufacturing partners.</div>

<div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Experience with AI accelerator or GPU form factors such as OAM and UBB, SXM, PCIe&nbsp;CEM cards, or OCP and DC-MHS compliant platforms, including liquid-cooled designs.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Signal and power integrity simulation experience with tools such as Cadence Sigrity,&nbsp;Ansys HFSS or SIwave, Keysight ADS, or HyperLynx, and the ability to interpret and act&nbsp;on extraction results.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Silicon and package co-design exposure: BGA escape planning, substrate and 2.5D or&nbsp;HBM package constraints, and joint debug with package and ASIC teams.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Post-silicon characterization experience including voltage and frequency margining and&nbsp;correlating lab measurements with ATE or emulation results.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Familiarity with FPGA prototyping platforms, socketed test boards, and interposer or&nbsp;riser based debug hardware.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Experience with thermal and mechanical co-design for high-power boards, including cold&nbsp;plates, heatsink loading, and board stiffening.<br>&nbsp;</div>

<div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Own the physical platform that our AI silicon runs on, where your board decisions&nbsp;directly determine whether the chip meets its performance, power, and reliability targets.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Work shoulder to shoulder with silicon, package, firmware, and validation engineers in a&nbsp;fast-moving team that values hands-on depth and measurement over guesswork.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Build hardware end to end, from the first bring-up fixture on a lab bench to a production&nbsp;accelerator platform, with real authority over architecture, vendor, and technology&nbsp;choices, and the scope to shape the board team as it grows.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Competitive compensation, growth opportunities, and the chance to help define the&nbsp;platform that powers advanced AI workloads.</div>

<div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">If you’re passionate about turning new silicon into working, measurable, manufacturable</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">hardware — we’d love to hear from you.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">Apply now and help us deliver production-ready platforms that make AI faster, safer, and more</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">efficient.</div>

Staff Hardware Board Design Engineer

<p>Location: Dubai - UAE</p><p>Team: Hardware Engineering – PCB Layout &amp; Signal Integrity</p><p>Type: Full-time – On-site</p>

<p><span style="background-color:rgb(255,255,255);color:rgb(0,0,0);font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;"><span style="-webkit-text-stroke-width:0px;display:inline !important;float:none;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;orphans:2;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">As a High-Speed PCB Layout Engineer, you will own the physical realization of our AI&nbsp;accelerator boards: the stackups, the escape routing out of large fine-pitch ASIC packages, the&nbsp;multi-gigabit channels, and the high-current power shapes that decide whether a design closes&nbsp;its loss and impedance budgets. You will work from schematics and constraint sets owned by&nbsp;our board design engineers and turn them into dense, manufacturable, high layer count PCBs,&nbsp;spanning both production accelerator platforms and the test boards used for silicon bring-up and&nbsp;characterization.</span></span></p>

<div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• High-density board layout ownership: own multi-layer PCB layouts end to end for AI&nbsp;accelerator cards, modules, system boards, and silicon test fixtures, from floorplanning&nbsp;and placement through routing, copper pour, and release.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• ASIC package escape and high-speed routing: execute escape routing for large, fine-&nbsp;pitch BGA and route multi-gigabit channels including PCIe Gen6, GDDR7, and&nbsp;400G/800G Ethernet links, applying HDI, via-in pad and VIPPO, blind and buried vias,&nbsp;backdrilling, and any-layer interconnect where needed.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Stackup, impedance, and material definition: define and negotiate layer stackups,&nbsp;dielectric materials, impedance targets, and loss budgets with fabricators, and select&nbsp;constructions that meet electrical, thermal, and cost objectives.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Constraint management and timing closure: build and maintain constraint sets in&nbsp;Cadence Allegro Constraint Manager, including differential pair phase tuning, delay and&nbsp;skew matching, T-topologies, Z-axis delay compensation, crosstalk control, and return-path continuity.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Power distribution layout: lay out high-current power delivery for accelerator-class&nbsp;devices, covering plane and shape partitioning, copper weight and thermal via strategy,decoupling placement, and PDN loop inductance minimization in coordination with&nbsp;power integrity engineers.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Simulation-driven iteration: work with signal and power integrity engineers to extract&nbsp;critical channels and planes, interpret results, and iterate placement, stackup, and&nbsp;routing until the design meets its margins.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Manufacturability and release: drive DFM, DFA, and DFT reviews with fab and&nbsp;assembly vendors, maintain footprint and padstack libraries and ECAD data integrity,&nbsp;and produce complete, unambiguous release packages in Gerber, ODB++, or IPC-2581.</div>

<div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Diploma, Bachelor’s, or equivalent qualification in Electrical or Electronics Engineering,&nbsp;or equivalent professional PCB design experience.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• 8+ years of high-speed, high-density PCB layout experience, with a strong focus on&nbsp;server, networking, or AI accelerator hardware.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Expert-level proficiency in Cadence Allegro including Constraint Manager; Altium&nbsp;Designer or Siemens Xpedition experience is a plus.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Proven track record laying out high layer count boards, ideally 16 layers and above,&nbsp;using HDI, sequential lamination, via-in-pad and VIPPO, blind and buried vias, and&nbsp;controlled-depth backdrilling.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Demonstrated routing of at least two of the following interface families to closure: PCIe&nbsp;Gen5/6, LPDDR5, GDDR6/7, HBM-adjacent interfaces, 400G/800G Ethernet.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Hands-on experience with escape routing from large, fine-pitch BGA packages and&nbsp;dense land grid footprints.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Solid grasp of stackup and material selection, impedance control, insertion loss&nbsp;budgeting, and how fabrication tolerances affect real channel performance.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Competence in high-current power plane layout, thermal via and copper weight&nbsp;decisions, and decoupling placement for PDN performance.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Working knowledge of IPC standards including IPC-2221, IPC-2222, IPC-6012, and&nbsp;IPC-7351, plus practical DFM, DFA, and DFT rule sets from real production builds.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Experience collaborating with signal and power integrity engineers, mechanical&nbsp;designers, and fabricators, including running layout and DFM reviews directly with&nbsp;vendors.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Strong communication and documentation skills, with the discipline to keep libraries,&nbsp;constraints, revisions, and release data clean and traceable.</div>

<div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• IPC CID or CID+ certification.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Automation and scripting experience with Allegro SKILL or equivalent to accelerate&nbsp;repetitive layout and checking tasks.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Direct use of extraction and simulation tools such as Cadence Sigrity and PowerSI,&nbsp;Ansys SIwave or HFSS, or Clarity, and the ability to close loops without waiting on a&nbsp;specialist.<br>• Experience with AI accelerator and data center form factors such as OAM, UBB, SXM,&nbsp;PCIe CEM, or OCP and DC-MHS compliant boards, including liquid-cooled and cold-plate constrained layouts.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Rigid-flex, press-fit connector, cable, and backplane or midplane layout experience.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Mechanical co-design fluency with STEP exchange and tools such as SolidWorks, Creo,&nbsp;or NX for tightly packaged, high-power assemblies.<br>&nbsp;</div>

<div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Route the boards that carry our own AI silicon, where your stackup and escape strategy&nbsp;decisions directly set the performance ceiling of the product.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Sit inside the engineering team rather than at the end of a handoff chain, working daily&nbsp;with board design, signal integrity, package, and mechanical engineers.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Take on genuinely hard layout problems, from dense ASIC package escapes to first-of-&nbsp;a-kind bring-up fixtures, with the tooling and vendor access to do them properly.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">• Competitive compensation, growth opportunities, and the chance to help define the&nbsp;platform that powers advanced AI workloads.</div>

<div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">If you’re passionate about closing impossible-looking channels and power planes on dense,</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">high layer count boards — we’d love to hear from you.</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">Apply now and help us deliver production-ready platforms that make AI faster, safer, and more</div><div style="-webkit-text-stroke-width:0px;background-color:rgb(255, 255, 255);border:0px solid rgb(229, 231, 235);box-sizing:border-box;color:black;font-family:Inter, &quot;Inter Fallback&quot;;font-size:13px;font-style:normal;font-variant-caps:normal;font-variant-ligatures:normal;font-weight:400;letter-spacing:normal;line-height:1.5;margin:0px;orphans:2;padding:0px;text-align:start;text-decoration-color:initial;text-decoration-style:initial;text-decoration-thickness:initial;text-indent:0px;text-transform:none;white-space:normal;widows:2;word-spacing:0px;">efficient.</div>

High-Speed PCB Layout Engineer

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At Evollabs, we foster curiosity, collaboration, and growth—giving you the space to innovate and shape what comes next. Join us and help build the future.

